Changeset 7f1c620 in mainline for arch/amd64/include/memstr.h
- Timestamp:
- 2006-07-04T17:17:56Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 0ffa3ef5
- Parents:
- 991779c5
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/amd64/include/memstr.h
r991779c5 r7f1c620 50 50 static inline void * memcpy(void * dst, const void * src, size_t cnt) 51 51 { 52 __natived0, d1, d2;52 unative_t d0, d1, d2; 53 53 54 54 __asm__ __volatile__( … … 60 60 "1:\n" 61 61 : "=&c" (d0), "=&D" (d1), "=&S" (d2) 62 : "0" (( __native)(cnt / 8)), "g" ((__native)cnt), "1" ((__native) dst), "2" ((__native) src)62 : "0" ((unative_t)(cnt / 8)), "g" ((unative_t)cnt), "1" ((unative_t) dst), "2" ((unative_t) src) 63 63 : "memory"); 64 64 … … 80 80 static inline int memcmp(const void * src, const void * dst, size_t cnt) 81 81 { 82 __natived0, d1, d2;83 __nativeret;82 unative_t d0, d1, d2; 83 unative_t ret; 84 84 85 85 __asm__ ( … … 90 90 "1:\n" 91 91 : "=a" (ret), "=%S" (d0), "=&D" (d1), "=&c" (d2) 92 : "0" (0), "1" (src), "2" (dst), "3" (( __native)cnt)92 : "0" (0), "1" (src), "2" (dst), "3" ((unative_t)cnt) 93 93 ); 94 94 … … 105 105 * @param x Value to fill 106 106 */ 107 static inline void memsetw( __address dst, size_t cnt, __u16x)107 static inline void memsetw(uintptr_t dst, size_t cnt, uint16_t x) 108 108 { 109 __natived0, d1;109 unative_t d0, d1; 110 110 111 111 __asm__ __volatile__ ( 112 112 "rep stosw\n\t" 113 113 : "=&D" (d0), "=&c" (d1), "=a" (x) 114 : "0" (dst), "1" (( __native)cnt), "2" (x)114 : "0" (dst), "1" ((unative_t)cnt), "2" (x) 115 115 : "memory" 116 116 ); … … 127 127 * @param x Value to fill 128 128 */ 129 static inline void memsetb( __address dst, size_t cnt, __u8x)129 static inline void memsetb(uintptr_t dst, size_t cnt, uint8_t x) 130 130 { 131 __natived0, d1;131 unative_t d0, d1; 132 132 133 133 __asm__ __volatile__ ( 134 134 "rep stosb\n\t" 135 135 : "=&D" (d0), "=&c" (d1), "=a" (x) 136 : "0" (dst), "1" (( __native)cnt), "2" (x)136 : "0" (dst), "1" ((unative_t)cnt), "2" (x) 137 137 : "memory" 138 138 );
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