Changeset 7f1c620 in mainline for arch/ia64/src/ia64.c
- Timestamp:
- 2006-07-04T17:17:56Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 0ffa3ef5
- Parents:
- 991779c5
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/ia64/src/ia64.c
r991779c5 r7f1c620 78 78 { 79 79 /* Set Interruption Vector Address (i.e. location of interruption vector table). */ 80 iva_write(( __address) &ivt);80 iva_write((uintptr_t) &ivt); 81 81 srlz_d(); 82 82 … … 117 117 rsc.mode = 3; /* eager mode */ 118 118 119 switch_to_userspace(( __address) kernel_uarg->uspace_entry,120 (( __address) kernel_uarg->uspace_stack)+PAGE_SIZE-ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT),121 (( __address) kernel_uarg->uspace_stack)+PAGE_SIZE,122 ( __address) kernel_uarg->uspace_uarg,119 switch_to_userspace((uintptr_t) kernel_uarg->uspace_entry, 120 ((uintptr_t) kernel_uarg->uspace_stack)+PAGE_SIZE-ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT), 121 ((uintptr_t) kernel_uarg->uspace_stack)+PAGE_SIZE, 122 (uintptr_t) kernel_uarg->uspace_uarg, 123 123 psr.value, rsc.value); 124 124 … … 132 132 * We use r13 (a.k.a. tp) for this purpose. 133 133 */ 134 __native sys_tls_set(__nativeaddr)134 unative_t sys_tls_set(unative_t addr) 135 135 { 136 136 return 0;
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