Changeset 7f1c620 in mainline for arch/mips32/include/cp0.h
- Timestamp:
- 2006-07-04T17:17:56Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 0ffa3ef5
- Parents:
- 991779c5
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/mips32/include/cp0.h
r991779c5 r7f1c620 64 64 #define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it)))) 65 65 66 #define GEN_READ_CP0(nm,reg) static inline __u32cp0_ ##nm##_read(void) \66 #define GEN_READ_CP0(nm,reg) static inline uint32_t cp0_ ##nm##_read(void) \ 67 67 { \ 68 __u32retval; \68 uint32_t retval; \ 69 69 asm("mfc0 %0, $" #reg : "=r"(retval)); \ 70 70 return retval; \ 71 71 } 72 72 73 #define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write( __u32val) \73 #define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write(uint32_t val) \ 74 74 { \ 75 75 asm("mtc0 %0, $" #reg : : "r"(val) ); \
Note:
See TracChangeset
for help on using the changeset viewer.