Changeset 7f1c620 in mainline for arch/sparc64/include/mm/tlb.h
- Timestamp:
- 2006-07-04T17:17:56Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 0ffa3ef5
- Parents:
- 991779c5
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/sparc64/include/mm/tlb.h
r991779c5 r7f1c620 57 57 58 58 union tlb_context_reg { 59 __u64v;59 uint64_t v; 60 60 struct { 61 61 unsigned long : 51; … … 70 70 /** I-/D-TLB Data Access Address in Alternate Space. */ 71 71 union tlb_data_access_addr { 72 __u64value;72 uint64_t value; 73 73 struct { 74 __u64: 55;74 uint64_t : 55; 75 75 unsigned tlb_entry : 6; 76 76 unsigned : 3; … … 82 82 /** I-/D-TLB Tag Read Register. */ 83 83 union tlb_tag_read_reg { 84 __u64value;84 uint64_t value; 85 85 struct { 86 __u64vpn : 51; /**< Virtual Address bits 63:13. */86 uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ 87 87 unsigned context : 13; /**< Context identifier. */ 88 88 } __attribute__ ((packed)); … … 102 102 /** TLB Demap Operation Address. */ 103 103 union tlb_demap_addr { 104 __u64value;104 uint64_t value; 105 105 struct { 106 __u64vpn: 51; /**< Virtual Address bits 63:13. */106 uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ 107 107 unsigned : 6; /**< Ignored. */ 108 108 unsigned type : 1; /**< The type of demap operation. */ … … 115 115 /** TLB Synchronous Fault Status Register. */ 116 116 union tlb_sfsr_reg { 117 __u64value;117 uint64_t value; 118 118 struct { 119 119 unsigned long : 39; /**< Implementation dependent. */ … … 137 137 * @return Current value of Primary Context Register. 138 138 */ 139 static inline __u64mmu_primary_context_read(void)139 static inline uint64_t mmu_primary_context_read(void) 140 140 { 141 141 return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); … … 146 146 * @param v New value of Primary Context Register. 147 147 */ 148 static inline void mmu_primary_context_write( __u64v)148 static inline void mmu_primary_context_write(uint64_t v) 149 149 { 150 150 asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); … … 156 156 * @return Current value of Secondary Context Register. 157 157 */ 158 static inline __u64mmu_secondary_context_read(void)158 static inline uint64_t mmu_secondary_context_read(void) 159 159 { 160 160 return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); … … 165 165 * @param v New value of Primary Context Register. 166 166 */ 167 static inline void mmu_secondary_context_write( __u64v)167 static inline void mmu_secondary_context_write(uint64_t v) 168 168 { 169 169 asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); … … 177 177 * @return Current value of specified IMMU TLB Data Access Register. 178 178 */ 179 static inline __u64itlb_data_access_read(index_t entry)179 static inline uint64_t itlb_data_access_read(index_t entry) 180 180 { 181 181 tlb_data_access_addr_t reg; … … 191 191 * @param value Value to be written. 192 192 */ 193 static inline void itlb_data_access_write(index_t entry, __u64value)193 static inline void itlb_data_access_write(index_t entry, uint64_t value) 194 194 { 195 195 tlb_data_access_addr_t reg; … … 207 207 * @return Current value of specified DMMU TLB Data Access Register. 208 208 */ 209 static inline __u64dtlb_data_access_read(index_t entry)209 static inline uint64_t dtlb_data_access_read(index_t entry) 210 210 { 211 211 tlb_data_access_addr_t reg; … … 221 221 * @param value Value to be written. 222 222 */ 223 static inline void dtlb_data_access_write(index_t entry, __u64value)223 static inline void dtlb_data_access_write(index_t entry, uint64_t value) 224 224 { 225 225 tlb_data_access_addr_t reg; … … 237 237 * @return Current value of specified IMMU TLB Tag Read Register. 238 238 */ 239 static inline __u64itlb_tag_read_read(index_t entry)239 static inline uint64_t itlb_tag_read_read(index_t entry) 240 240 { 241 241 tlb_tag_read_addr_t tag; … … 252 252 * @return Current value of specified DMMU TLB Tag Read Register. 253 253 */ 254 static inline __u64dtlb_tag_read_read(index_t entry)254 static inline uint64_t dtlb_tag_read_read(index_t entry) 255 255 { 256 256 tlb_tag_read_addr_t tag; … … 265 265 * @param v Value to be written. 266 266 */ 267 static inline void itlb_tag_access_write( __u64v)267 static inline void itlb_tag_access_write(uint64_t v) 268 268 { 269 269 asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); … … 275 275 * @return Current value of IMMU TLB Tag Access Register. 276 276 */ 277 static inline __u64itlb_tag_access_read(void)277 static inline uint64_t itlb_tag_access_read(void) 278 278 { 279 279 return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); … … 284 284 * @param v Value to be written. 285 285 */ 286 static inline void dtlb_tag_access_write( __u64v)286 static inline void dtlb_tag_access_write(uint64_t v) 287 287 { 288 288 asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); … … 294 294 * @return Current value of DMMU TLB Tag Access Register. 295 295 */ 296 static inline __u64dtlb_tag_access_read(void)296 static inline uint64_t dtlb_tag_access_read(void) 297 297 { 298 298 return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); … … 304 304 * @param v Value to be written. 305 305 */ 306 static inline void itlb_data_in_write( __u64v)306 static inline void itlb_data_in_write(uint64_t v) 307 307 { 308 308 asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); … … 314 314 * @param v Value to be written. 315 315 */ 316 static inline void dtlb_data_in_write( __u64v)316 static inline void dtlb_data_in_write(uint64_t v) 317 317 { 318 318 asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); … … 324 324 * @return Current content of I-SFSR register. 325 325 */ 326 static inline __u64itlb_sfsr_read(void)326 static inline uint64_t itlb_sfsr_read(void) 327 327 { 328 328 return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); … … 333 333 * @param v New value of I-SFSR register. 334 334 */ 335 static inline void itlb_sfsr_write( __u64v)335 static inline void itlb_sfsr_write(uint64_t v) 336 336 { 337 337 asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); … … 343 343 * @return Current content of D-SFSR register. 344 344 */ 345 static inline __u64dtlb_sfsr_read(void)345 static inline uint64_t dtlb_sfsr_read(void) 346 346 { 347 347 return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); … … 352 352 * @param v New value of D-SFSR register. 353 353 */ 354 static inline void dtlb_sfsr_write( __u64v)354 static inline void dtlb_sfsr_write(uint64_t v) 355 355 { 356 356 asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); … … 362 362 * @return Current content of D-SFAR register. 363 363 */ 364 static inline __u64dtlb_sfar_read(void)364 static inline uint64_t dtlb_sfar_read(void) 365 365 { 366 366 return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); … … 373 373 * @param page Address which is on the page to be demapped. 374 374 */ 375 static inline void itlb_demap(int type, int context_encoding, __addresspage)375 static inline void itlb_demap(int type, int context_encoding, uintptr_t page) 376 376 { 377 377 tlb_demap_addr_t da; … … 395 395 * @param page Address which is on the page to be demapped. 396 396 */ 397 static inline void dtlb_demap(int type, int context_encoding, __addresspage)397 static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) 398 398 { 399 399 tlb_demap_addr_t da; … … 415 415 extern void fast_data_access_protection(void); 416 416 417 extern void dtlb_insert_mapping( __address page, __addressframe, int pagesize, bool locked, bool cacheable);417 extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable); 418 418 419 419 #endif
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