Changeset 807be7e in mainline


Ignore:
Timestamp:
2020-05-17T16:52:19Z (5 years ago)
Author:
jxsvoboda <5887334+jxsvoboda@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
145a13b
Parents:
0800b26
git-author:
Colin Parker <cvparker@…> (2020-05-10 18:45:27)
git-committer:
jxsvoboda <5887334+jxsvoboda@…> (2020-05-17 16:52:19)
Message:

Mask the ICR register in the interrupt claim pseudo-code to prevent
false interrupt claims when masked-out ICR causes are true.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • uspace/drv/nic/e1k/e1k.c

    r0800b26 r807be7e  
    256256        },
    257257        {
     258                .cmd = CMD_AND,
     259                .value = ICR_RXT0,
     260                .srcarg = 2,
     261                .dstarg = 1
     262        },
     263        {
    258264                .cmd = CMD_PREDICATE,
    259265                .value = 2,
    260                 .srcarg = 2
     266                .srcarg = 1
    261267        },
    262268        {
     
    12741280        e1000_irq_code.ranges[0].base = (uintptr_t) e1000->reg_base_phys;
    12751281        e1000_irq_code.cmds[0].addr = e1000->reg_base_phys + E1000_ICR;
    1276         e1000_irq_code.cmds[2].addr = e1000->reg_base_phys + E1000_IMC;
     1282        e1000_irq_code.cmds[3].addr = e1000->reg_base_phys + E1000_IMC;
    12771283
    12781284        errno_t rc = register_interrupt_handler(nic_get_ddf_dev(nic), e1000->irq,
Note: See TracChangeset for help on using the changeset viewer.