Changeset 80dabb8d in mainline for kernel/generic/src/mm/page.c

Timestamp:

2008-06-12T07:49:23Z (16 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

e25eca80

Parents:

11e9061d

Message:

Add a comment explaining the reason for a memory barrier after page table update in detail.

File:

• kernel/generic/src/mm/page.c (modified) (1 diff)

kernel/generic/src/mm/page.c

@@ -39 +39 @@
  * Functions here are mere wrappers that call the real implementation.
  * They however, define the single interface. 
+ */
+
+/*
+ * Note on memory prefetching and updating memory mappings, also described in:
+ * AMD x86-64 Architecture Programmer's Manual, Volume 2, System Programming,
+ * 7.2.1 Special Coherency Considerations.
+ *
+ * The processor which modifies a page table mapping can access prefetched data
+ * from the old mapping.  In order to prevent this, we place a memory barrier
+ * after a mapping is updated.
+ *
+ * We assume that the other processors are either not using the mapping yet
+ * (i.e. during the bootstrap) or are executing the TLB shootdown code.  While
+ * we don't care much about the former case, the processors in the latter case 
+ * will do an implicit serialization by virtue of running the TLB shootdown
+ * interrupt handler.
  */