Changeset 83817ea in mainline

Timestamp:

2005-11-07T15:10:49Z (19 years ago)

Author:

Jakub Vana <jakub.vana@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

a725deb

Parents:

17a20bc

Message:

Context restore in HEAVYWEIGHT handlers

Location:

arch/ia64

Files:

• include/stack.h (modified) (1 diff)
• src/interrupt.c (modified) (1 diff)
• src/ivt.S (modified) (1 diff)

arch/ia64/include/stack.h

@@ -30 +30 @@
 #define __ia64_STACK_H__
 
-#define STACK_ITEM_SIZE                 16
+#define STACK_ITEM_SIZE                 8
 #define STACK_ALIGNMENT                 16
 #define STACK_SCRATCH_AREA_SIZE         16

arch/ia64/src/interrupt.c

@@ -44 +44 @@
         ivr.value = ivr_read();
         srlz_d();
-        
+
+/*      printf("Interrupr\n");
+*/      
         switch(ivr.vector) {
             case INTERRUPT_TIMER:
                 it_interrupt();
-                panic("cpu%d: timer interrupt\n", CPU->id);
                 break;
             case INTERRUPT_SPURIOUS:

arch/ia64/src/ivt.S

@@ -256 +256 @@
 heavyweight_handler_finalize:
     /* 16. RSE switch to interrupted context */
-        
+
+/********************************************************************************************/
+
+
+
+        .auto
+        cover                   /*Allocate zerro size frame (Step 1(from Intel Docs))*/
+
+        add r31 = STACK_SCRATCH_AREA_SIZE, r12;;
+
+        mov r28 = ar.bspstore   /*Calculate loadrs (step 2)*/
+        ld8 r29 = [r31], +8     
+        sub r27 = r29 , r28
+        shl r27 = r27, 16
+
+        mov r24 = ar.rsc
+        and r30 = ~3, r24
+        or  r24 = r30 , r27     
+        mov ar.rsc = r24        /* place RSE in enforced lazy mode */
+
+
+
+        loadrs                  /*(Step 3)*/
+
+
+                                /*Read saved registers*/
+        ld8 r28 = [r31], +8     /*ar.bspstore*/
+        ld8 r27 = [r31], +8     /*ar.rnat*/
+        ld8 r26 = [r31], +8     /*cr.ifs*/
+        ld8 r25 = [r31], +8     /*ar.pfs*/
+        ld8 r24 = [r31], +8     /*ar.rsc*/
+
+
+        mov ar.bspstore = r28   /*(Step 4)*/
+        mov ar.rnat = r27       /*(Step 5)*/
+
+        mov ar.pfs = r25        /*(Step 6)*/
+        mov cr.ifs = r26        
+
+        mov ar.rsc = r24        /*(Step 7)*/
+
+
+        .explicit       
+
+
+/********************************************************************************************/
+
+
+
     /* 17. restore interruption state from memory stack */
+
+        ld8 r28 = [r31] , +8 ;; /* load cr.ifa */               
+        ld8 r27 = [r31] , +8 ;; /* load cr.isr */
+        ld8 r26 = [r31] , +8 ;; /* load cr.iipa */
+        ld8 r25 = [r31] , +8 ;; /* load cr.ipsr */
+        ld8 r24 = [r31] , +8 ;; /* load cr.iip */
+
+
+        mov cr.iip = r24
+        mov cr.ipsr = r25
+        mov cr.iipa = r26
+        mov cr.isr = r27
+        mov cr.ifa = r28
+
+
         
     /* 18. restore predicate registers from memory stack */
+
+
+        ld8 r29 = [r31] , -8 ;; /* load predicate registers */
+        mov pr =r29 ;;
+        
+        add r12 = STACK_FRAME_SIZE,r12;;
         
     /* 19. return from interruption */
-        rfi
-
-
+        rfi;;