Changeset 8440473 in mainline for kernel/arch/sparc64/include/trap/mmu.h

Timestamp:

2006-10-26T21:36:32Z (18 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

8c84448

Parents:

19dce27

Message:

Minor changes. Some coding style fixes and also a type (tee vs. tree).
One AS → as change.

File:

• kernel/arch/sparc64/include/trap/mmu.h (modified) (2 diffs)

kernel/arch/sparc64/include/trap/mmu.h

@@ -61 +61 @@
          * First, try to refill TLB from TSB.
          */
-
 #ifdef CONFIG_TSB
         ldxa [%g0] ASI_IMMU, %g1                        ! read TSB Tag Target Register
@@ -85 +84 @@
 #ifdef CONFIG_TSB
         ldxa [%g0] ASI_DMMU, %g1                        ! read TSB Tag Target Register
-        srlx %g1, TSB_TAG_TARGET_CONTEXT_SHIFT, %g2     ! is this kernel miss?
+        srlx %g1, TSB_TAG_TARGET_CONTEXT_SHIFT, %g2     ! is this a kernel miss?
         brz,pn %g2, 0f
         ldxa [%g0] ASI_DMMU_TSB_8KB_PTR_REG, %g3        ! read TSB 8K Pointer