Changeset 876160ca in mainline

Timestamp:

2012-12-30T14:39:58Z (12 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

46a6a5d

Parents:

e7b0b85

Message:

arm32, boot: LImit chache enabling to Cortex-A8 MPU.

Cache behavior is not mandated by arch.

File:

• boot/arch/arm32/src/mm.c (modified) (1 diff)

boot/arch/arm32/src/mm.c

@@ -119 +119 @@
                 "mrc p15, 0, r0, c1, c0, 0\n"
                 
-#ifdef PROCESSOR_ARCH_armv7_a
+#ifdef PROCESSOR_cortex_a8
                 /* Mask to enable paging, I-cache D-cache and branch predict
-                 * See kernel/arch/arm32/include/regutils.h for bit values.*/
+                 * See kernel/arch/arm32/include/regutils.h for bit values.
+                 * It's safe because Cortex-A8 implements IVIPT extension
+                 * See Cortex-A8 TRM ch. 7.2.6 p. 7-4 (PDF 245) */
                 "ldr r1, =0x00001805\n"
 #else
-                /* Mask to enable paging */
-                "ldr r1, =0x00000001\n"
+                /* Mask to enable paging and branch prediction */
+                "ldr r1, =0x00000801\n"
 #endif
                 "orr r0, r0, r1\n"