Changeset 897ad60 in mainline for arch/amd64/src/pm.c
- Timestamp:
- 2006-04-13T16:11:27Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 39cea6a
- Parents:
- 963074b3
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/amd64/src/pm.c
r963074b3 r897ad60 216 216 gdt_tss_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1); 217 217 218 __asm__("lgdt %0" : : "m"(gdtr));219 __asm__("lidt %0" : : "m"(idtr));218 gdtr_load(&gdtr); 219 idtr_load(&idtr); 220 220 /* 221 221 * As of this moment, the current CPU has its own GDT pointing 222 222 * to its own TSS. We just need to load the TR register. 223 223 */ 224 __asm__("ltr %0" : : "r" ((__u16) gdtselector(TSS_DES)));225 } 224 tr_load(gdtselector(TSS_DES)); 225 }
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