Changeset 8addb24a in mainline
- Timestamp:
- 2023-02-03T17:01:49Z (22 months ago)
- Branches:
- master, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- aae2869
- Parents:
- 64e9cf4
- Location:
- kernel
- Files:
-
- 11 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/abs32le/include/arch/asm.h
r64e9cf4 r8addb24a 67 67 } 68 68 69 _NO_TRACE static inline void cpu_spin_hint(void) 70 { 71 /* 72 * Some ISAs have a special instruction for the body of a busy wait loop, 73 * such as in spinlock and the like. Using it allows the CPU to optimize 74 * its operation. For an example, see the "pause" instruction on x86. 75 */ 76 } 77 69 78 _NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val) 70 79 { -
kernel/arch/amd64/include/arch/asm.h
r64e9cf4 r8addb24a 59 59 } 60 60 61 #define ARCH_SPIN_HINT() asm volatile ("pause\n") 61 _NO_TRACE static inline void cpu_spin_hint(void) 62 { 63 asm volatile ( 64 "pause\n" 65 ); 66 } 62 67 63 68 /** Byte from port -
kernel/arch/arm32/include/arch/asm.h
r64e9cf4 r8addb24a 65 65 } 66 66 67 _NO_TRACE static inline void cpu_spin_hint(void) 68 { 67 69 #ifdef PROCESSOR_ARCH_armv7_a 68 #define ARCH_SPIN_HINT() asm volatile ("yield") 70 asm volatile ("yield"); 69 71 #endif 72 } 70 73 71 74 _NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v) -
kernel/arch/arm64/include/arch/asm.h
r64e9cf4 r8addb24a 61 61 } 62 62 63 #define ARCH_SPIN_HINT() asm volatile ("yield") 63 _NO_TRACE static inline void cpu_spin_hint(void) 64 { 65 asm volatile ("yield"); 66 } 64 67 65 68 /** Output byte to port. -
kernel/arch/ia32/include/arch/asm.h
r64e9cf4 r8addb24a 64 64 } 65 65 66 #define ARCH_SPIN_HINT() asm volatile ("pause\n") 66 _NO_TRACE static inline void cpu_spin_hint(void) 67 { 68 asm volatile ( 69 "pause\n" 70 ); 71 } 67 72 68 73 #define GEN_READ_REG(reg) _NO_TRACE static inline sysarg_t read_ ##reg (void) \ -
kernel/arch/ia64/include/arch/asm.h
r64e9cf4 r8addb24a 44 44 #define IO_SPACE_BOUNDARY ((void *) (64 * 1024)) 45 45 46 _NO_TRACE static inline void cpu_spin_hint(void) 47 { 48 } 49 46 50 /** Map the I/O port address to a legacy I/O address. */ 47 51 _NO_TRACE static inline uintptr_t p2a(volatile void *p) -
kernel/arch/mips32/include/arch/asm.h
r64e9cf4 r8addb24a 45 45 } 46 46 47 _NO_TRACE static inline void cpu_spin_hint(void) 48 { 49 } 50 47 51 _NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v) 48 52 { -
kernel/arch/ppc32/include/arch/asm.h
r64e9cf4 r8addb24a 42 42 #include <trace.h> 43 43 44 _NO_TRACE static inline void cpu_spin_hint(void) 45 { 46 } 47 44 48 _NO_TRACE static inline uint32_t msr_read(void) 45 49 { -
kernel/arch/riscv64/include/arch/asm.h
r64e9cf4 r8addb24a 41 41 #include <arch/mm/asid.h> 42 42 #include <trace.h> 43 44 _NO_TRACE static inline void cpu_spin_hint(void) 45 { 46 } 43 47 44 48 _NO_TRACE static inline ipl_t interrupts_enable(void) -
kernel/arch/sparc64/include/arch/asm.h
r64e9cf4 r8addb24a 44 44 #include <trace.h> 45 45 46 _NO_TRACE static inline void cpu_spin_hint(void) 47 { 48 } 49 46 50 _NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v) 47 51 { -
kernel/generic/src/synch/spinlock.c
r64e9cf4 r8addb24a 49 49 #include <cpu.h> 50 50 51 #ifndef ARCH_SPIN_HINT52 #define ARCH_SPIN_HINT() ((void)0)53 #endif54 55 51 /** Initialize spinlock 56 52 * … … 82 78 83 79 while (atomic_flag_test_and_set_explicit(&lock->flag, memory_order_acquire)) { 84 ARCH_SPIN_HINT();80 cpu_spin_hint(); 85 81 86 82 #ifdef CONFIG_DEBUG_SPINLOCK
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