Changes in uspace/drv/bus/usb/uhci/hc.c [e6b9182:8d2dd7f2] in mainline
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uspace/drv/bus/usb/uhci/hc.c
re6b9182 r8d2dd7f2 50 50 #include <usb/usb.h> 51 51 #include <usb/host/utils/malloc32.h> 52 #include <usb/host/bandwidth.h>53 52 54 53 #include "uhci_batch.h" … … 107 106 * @return Error code. 108 107 */ 109 int uhci_hc_gen_irq_code(irq_code_t *code, hcd_t *hcd,const hw_res_list_parsed_t *hw_res)108 int uhci_hc_gen_irq_code(irq_code_t *code, const hw_res_list_parsed_t *hw_res) 110 109 { 111 110 assert(code); … … 215 214 * interrupt fibrils. 216 215 */ 217 int hc_init(hc_t *instance, const hw_res_list_parsed_t *hw_res )216 int hc_init(hc_t *instance, const hw_res_list_parsed_t *hw_res, bool interrupts) 218 217 { 219 218 assert(instance); … … 223 222 return EINVAL; 224 223 224 instance->hw_interrupts = interrupts; 225 225 instance->hw_failures = 0; 226 226 … … 246 246 } 247 247 248 return EOK;249 }250 251 void hc_start(hc_t *instance)252 {253 248 hc_init_hw(instance); 254 249 (void)hc_debug_checker; 255 250 256 251 uhci_rh_init(&instance->rh, instance->registers->ports, "uhci"); 252 253 return EOK; 257 254 } 258 255 … … 321 318 int hc_init_mem_structures(hc_t *instance) 322 319 { 323 int err; 324 assert(instance); 325 326 if ((err = usb2_bus_init(&instance->bus, BANDWIDTH_AVAILABLE_USB11, bandwidth_count_usb11))) 327 return err; 320 assert(instance); 328 321 329 322 /* Init USB frame list page */ … … 447 440 assert(batch); 448 441 449 if (batch->ep-> target.address == uhci_rh_get_address(&instance->rh))442 if (batch->ep->address == uhci_rh_get_address(&instance->rh)) 450 443 return uhci_rh_schedule(&instance->rh, batch); 451 444
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