Changeset 8ff0bd2 in mainline for kernel/arch/mips32/include/cp0.h

Timestamp:

2011-09-04T11:30:58Z (14 years ago)

Author:

Maurizio Lombardi <m.lombardi85@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

03bc76a

Parents:

d2c67e7 (diff), deac215e (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge mainline changes

File:

• kernel/arch/mips32/include/cp0.h (modified) (2 diffs)

kernel/arch/mips32/include/cp0.h

@@ -36 +36 @@
 #define KERN_mips32_CP0_H_
 
-#ifdef KERNEL
-#include <typedefs.h>
-#else
-#include <sys/types.h>
-#endif
-
 #define cp0_status_ie_enabled_bit     (1 << 0)
 #define cp0_status_exl_exception_bit  (1 << 1)
@@ -49 +43 @@
 #define cp0_status_fpu_bit            (1 << 29)
 
-#define cp0_status_im_shift             8
-#define cp0_status_im_mask              0xff00
+#define cp0_status_im_shift  8
+#define cp0_status_im_mask   0xff00
 
-#define cp0_cause_excno(cause) ((cause >> 2) & 0x1f)
-#define cp0_cause_coperr(cause) ((cause >> 28) & 0x3)
+#define cp0_cause_excno(cause)   ((cause >> 2) & 0x1f)
+#define cp0_cause_coperr(cause)  ((cause >> 28) & 0x3)
 
-#define fpu_cop_id 1
+#define fpu_cop_id  1
 
 /*
  * Magic value for use in msim.
  */
-#define cp0_compare_value               100000
+#define cp0_compare_value  100000
 
-#define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
-#define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask)
-#define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1 << (cp0_status_im_shift + (it))))
-#define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1 << (cp0_status_im_shift + (it))))
+#define cp0_mask_all_int() \
+        cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
 
-#define GEN_READ_CP0(nm,reg) static inline uint32_t cp0_ ##nm##_read(void) \
-  { \
-      uint32_t retval; \
-      asm volatile ("mfc0 %0, $" #reg : "=r"(retval)); \
-      return retval; \
-  }
+#define cp0_unmask_all_int() \
+        cp0_status_write(cp0_status_read() | cp0_status_im_mask)
 
-#define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write(uint32_t val) \
- { \
-    asm volatile ("mtc0 %0, $" #reg : : "r"(val) ); \
- }
+#define cp0_mask_int(it) \
+        cp0_status_write(cp0_status_read() & ~(1 << (cp0_status_im_shift + (it))))
+
+#define cp0_unmask_int(it) \
+        cp0_status_write(cp0_status_read() | (1 << (cp0_status_im_shift + (it))))
+
+#define GEN_READ_CP0(nm, reg) \
+        static inline uint32_t cp0_ ##nm##_read(void) \
+        { \
+                uint32_t retval; \
+                \
+                asm volatile ( \
+                        "mfc0 %0, $" #reg \
+                        : "=r"(retval) \
+                ); \
+                \
+                return retval; \
+        }
+
+#define GEN_WRITE_CP0(nm, reg) \
+        static inline void cp0_ ##nm##_write(uint32_t val) \
+        { \
+                asm volatile ( \
+                        "mtc0 %0, $" #reg \
+                        :: "r"(val) \
+                ); \
+        }
 
 GEN_READ_CP0(index, 0);