Changeset 909c6e3 in mainline for arch/mips/src/exception.c

Timestamp:

2005-09-07T09:44:30Z (19 years ago)

Author:

Ondrej Palkovsky <ondrap@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

d246e7e

Parents:

24bd23a

Message:

MIPS exception now saves all necesssary information only on stack.

File:

• arch/mips/src/exception.c (modified) (4 diffs)

arch/mips/src/exception.c

@@ -35 +35 @@
 #include <debug.h>
 
-void exception(void)
+void exception(struct exception_regdump *pstate)
 {
         int excno;
-        __u32 epc;
         __u32 epc_shift = 0;
 
@@ -46 +45 @@
          * NOTE ON OPERATION ORDERING
          *
-         * On entry, cpu_priority_high() must be called before exception bit is cleared.
-         * On exit, exception bit must be set before cpu_priority_restore() is called.
+         * On entry, cpu_priority_high() must be called before 
+         * exception bit is cleared.
          */
 
         cpu_priority_high();
-        epc = cp0_epc_read();
         cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit |
                                                 cp0_status_um_bit));
 
-        if (THREAD) {
-                THREAD->saved_epc = epc;
-        }
         /* decode exception number and process the exception */
         switch (excno = (cp0_cause_read() >> 2) & 0x1f) {
@@ -65 +60 @@
                 case EXC_TLBL:
                 case EXC_TLBS:
-                        tlb_invalid();
+                        tlb_invalid(pstate);
                         break;
                 case EXC_Mod:
@@ -115 +110 @@
         }
         
-        if (THREAD)
-                epc = THREAD->saved_epc;
-        
-        /* Raise EXL bit before epc_write, so that we support
-         * properly nested exceptions
-         */
-        cp0_status_write(cp0_status_read() | cp0_status_exl_exception_bit);
-        cp0_epc_write(epc + epc_shift);
+        pstate->epc += epc_shift;
 }