Changeset 91befde0 in mainline


Ignore:
Timestamp:
2008-09-08T20:30:20Z (16 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
c867756e
Parents:
bd83ccea
Message:

cstyle for mips32's tlb.c

File:
1 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/mips32/src/mm/tlb.c

    rbd83ccea r91befde0  
    4848#include <interrupt.h>
    4949
    50 static void tlb_refill_fail(istate_t *istate);
    51 static void tlb_invalid_fail(istate_t *istate);
    52 static void tlb_modified_fail(istate_t *istate);
    53 
    54 static pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate, int *pfrc);
    55 
    56 /** Initialize TLB
    57  *
    58  * Initialize TLB.
     50static void tlb_refill_fail(istate_t *);
     51static void tlb_invalid_fail(istate_t *);
     52static void tlb_modified_fail(istate_t *);
     53
     54static pte_t *find_mapping_and_check(uintptr_t, int, istate_t *, int *);
     55
     56/** Initialize TLB.
     57 *
    5958 * Invalidate all entries and mark wired entries.
    6059 */
    … …  
    8281}
    8382
    84 /** Process TLB Refill Exception
    85  *
    86  * Process TLB Refill Exception.
    87  *
    88  * @param istate Interrupted register context.
     83/** Process TLB Refill Exception.
     84 *
     85 * @param istate        Interrupted register context.
    8986 */
    9087void tlb_refill(istate_t *istate)
    … …  
    129126
    130127        tlb_prepare_entry_hi(&hi, asid, badvaddr);
    131         tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
     128        tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,
     129            pte->pfn);
    132130
    133131        /*
    … …  
    135133         */
    136134        cp0_entry_hi_write(hi.value);
    137         if ((badvaddr/PAGE_SIZE) % 2 == 0) {
     135        if ((badvaddr / PAGE_SIZE) % 2 == 0) {
    138136                cp0_entry_lo0_write(lo.value);
    139137                cp0_entry_lo1_write(0);
    … …  
    154152}
    155153
    156 /** Process TLB Invalid Exception
    157  *
    158  * Process TLB Invalid Exception.
    159  *
    160  * @param istate Interrupted register context.
     154/** Process TLB Invalid Exception.
     155 *
     156 * @param istate        Interrupted register context.
    161157 */
    162158void tlb_invalid(istate_t *istate)
    … …  
    218214        pte->a = 1;
    219215
    220         tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
     216        tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,
     217            pte->pfn);
    221218
    222219        /*
    223220         * The entry is to be updated in TLB.
    224221         */
    225         if ((badvaddr/PAGE_SIZE) % 2 == 0)
     222        if ((badvaddr / PAGE_SIZE) % 2 == 0)
    226223                cp0_entry_lo0_write(lo.value);
    227224        else
    … …  
    238235}
    239236
    240 /** Process TLB Modified Exception
    241  *
    242  * Process TLB Modified Exception.
    243  *
    244  * @param istate Interrupted register context.
     237/** Process TLB Modified Exception.
     238 *
     239 * @param istate        Interrupted register context.
    245240 */
    246241void tlb_modified(istate_t *istate)
    … …  
    309304        pte->d = 1;
    310305
    311         tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn);
     306        tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable,
     307            pte->pfn);
    312308
    313309        /*
    314310         * The entry is to be updated in TLB.
    315311         */
    316         if ((badvaddr/PAGE_SIZE) % 2 == 0)
     312        if ((badvaddr / PAGE_SIZE) % 2 == 0)
    317313                cp0_entry_lo0_write(lo.value);
    318314        else
    … …  
    341337                sym2 = s;
    342338
    343         fault_if_from_uspace(istate, "TLB Refill Exception on %p", cp0_badvaddr_read());
    344         panic("%x: TLB Refill Exception at %x(%s<-%s)\n", cp0_badvaddr_read(), istate->epc, symbol, sym2);
     339        fault_if_from_uspace(istate, "TLB Refill Exception on %p",
     340            cp0_badvaddr_read());
     341        panic("%x: TLB Refill Exception at %x(%s<-%s)\n", cp0_badvaddr_read(),
     342            istate->epc, symbol, sym2);
    345343}
    346344
    … …  
    353351        if (s)
    354352                symbol = s;
    355         fault_if_from_uspace(istate, "TLB Invalid Exception on %p", cp0_badvaddr_read());
    356         panic("%x: TLB Invalid Exception at %x(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);
     353        fault_if_from_uspace(istate, "TLB Invalid Exception on %p",
     354            cp0_badvaddr_read());
     355        panic("%x: TLB Invalid Exception at %x(%s)\n", cp0_badvaddr_read(),
     356            istate->epc, symbol);
    357357}
    358358
    … …  
    364364        if (s)
    365365                symbol = s;
    366         fault_if_from_uspace(istate, "TLB Modified Exception on %p", cp0_badvaddr_read());
    367         panic("%x: TLB Modified Exception at %x(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);
    368 }
    369 
    370 /** Try to find PTE for faulting address
    371  *
    372  * Try to find PTE for faulting address.
     366        fault_if_from_uspace(istate, "TLB Modified Exception on %p",
     367            cp0_badvaddr_read());
     368        panic("%x: TLB Modified Exception at %x(%s)\n", cp0_badvaddr_read(),
     369            istate->epc, symbol);
     370}
     371
     372/** Try to find PTE for faulting address.
     373 *
    373374 * The AS->lock must be held on entry to this function.
    374375 *
    375  * @param badvaddr Faulting virtual address.
    376  * @param access Access mode that caused the fault.
    377  * @param istate Pointer to interrupted state.
    378  * @param pfrc Pointer to variable where as_page_fault() return code will be stored.
    379  *
    380  * @return PTE on success, NULL otherwise.
    381  */
    382 pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate, int *pfrc)
     376 * @param badvaddr      Faulting virtual address.
     377 * @param access        Access mode that caused the fault.
     378 * @param istate        Pointer to interrupted state.
     379 * @param pfrc          Pointer to variable where as_page_fault() return code
     380 *                      will be stored.
     381 *
     382 * @return              PTE on success, NULL otherwise.
     383 */
     384pte_t *
     385find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate,
     386    int *pfrc)
    383387{
    384388        entry_hi_t hi;
    … …  
    442446}
    443447
    444 void tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn)
     448void
     449tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable,
     450    uintptr_t pfn)
    445451{
    446452        lo->value = 0;
    … …  
    481487               
    482488                printf("%-2u %-4u %#6x %#4x %1u %1u %1u %1u %#6x\n",
    483                         i, hi.asid, hi.vpn2, mask.mask,
    484                         lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn);
     489                    i, hi.asid, hi.vpn2, mask.mask,
     490                    lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn);
    485491                printf("                    %1u %1u %1u %1u %#6x\n",
    486                         lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
     492                    lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
    487493        }
    488494       
    … …  
    561567}
    562568
    563 /** Invalidate TLB entries for specified page range belonging to specified address space.
    564  *
    565  * @param asid Address space identifier.
    566  * @param page First page whose TLB entry is to be invalidated.
    567  * @param cnt Number of entries to invalidate.
     569/** Invalidate TLB entries for specified page range belonging to specified
     570 * address space.
     571 *
     572 * @param asid          Address space identifier.
     573 * @param page          First page whose TLB entry is to be invalidated.
     574 * @param cnt           Number of entries to invalidate.
    568575 */
    569576void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
    … …  
    589596
    590597                if (!index.p) {
    591                         /* Entry was found, index register contains valid index. */
     598                        /*
     599                         * Entry was found, index register contains valid
     600                         * index.
     601                         */
    592602                        tlbr();
    593603
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