Changeset 92d5279 in mainline

Timestamp:

2016-10-26T20:27:12Z (8 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

6c34be69

Parents:

9191607

Message:

pciintel: Support alternate method to access PCI configuration space

On UltraSPARC IIi-based machines, the PCI configuration space is mapped
directly in the portion of the PBM (PCI Bus Interface Module) address
space. It is therefore not accessed indirectly via the config address
and config data registers but directly by accessing the respective
portion of the PBM address space.

Location:

uspace/drv/bus/pci/pciintel

Files:

• pci.c (modified) (7 diffs)
• pci.h (modified) (1 diff)

uspace/drv/bus/pci/pciintel/pci.c

@@ -63 +63 @@
 #define NAME "pciintel"
 
+#define CONF_ADDR_ENABLE        (1 << 31)
 #define CONF_ADDR(bus, dev, fn, reg) \
-        ((1 << 31) | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
+        ((bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
 
 /** Obtain PCI function soft-state from DDF function node */
@@ -232 +233 @@
         fibril_mutex_lock(&bus->conf_mutex);
 
-        pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr));
-
-        /*
-         * Always read full 32-bits from the PCI conf_data_port register and
-         * get the desired portion of it afterwards. Some architectures do not
-         * support shorter PIO reads offset from this register.
-         */
-        val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
+        if (bus->conf_addr_reg) {
+                pio_write_32(bus->conf_addr_reg,
+                    host2uint32_t_le(CONF_ADDR_ENABLE | conf_addr));
+                /*
+                 * Always read full 32-bits from the PCI conf_data_port
+                 * register and get the desired portion of it afterwards. Some
+                 * architectures do not support shorter PIO reads offset from
+                 * this register.
+                 */
+                val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
+        } else {
+                val = uint32_t_le2host(pio_read_32(
+                    &bus->conf_space[conf_addr / sizeof(ioport32_t)]));
+        }
 
         switch (len) {
@@ -260 +267 @@
         const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
         pci_bus_t *bus = pci_bus_from_fun(fun);
-        uint32_t val = 0; // Prevent -Werror=maybe-uninitialized
+        uint32_t val;
         
         fibril_mutex_lock(&bus->conf_mutex);
@@ -275 +282 @@
                  * missing bits first.
                  */
-                pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr));
-                val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
+                if (bus->conf_addr_reg) {
+                        pio_write_32(bus->conf_addr_reg,
+                            host2uint32_t_le(CONF_ADDR_ENABLE | conf_addr));
+                        val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
+                } else {
+                        val = uint32_t_le2host(pio_read_32(
+                            &bus->conf_space[conf_addr / sizeof(ioport32_t)]));
+                }
         }
         
@@ -293 +306 @@
         }
 
-        pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr));
-        pio_write_32(bus->conf_data_reg, host2uint32_t_le(val));
+        if (bus->conf_addr_reg) {
+                pio_write_32(bus->conf_addr_reg,
+                    host2uint32_t_le(CONF_ADDR_ENABLE | conf_addr));
+                pio_write_32(bus->conf_data_reg, host2uint32_t_le(val));
+        } else {
+                pio_write_32(&bus->conf_space[conf_addr / sizeof(ioport32_t)],
+                    host2uint32_t_le(val));
+        }
         
         fibril_mutex_unlock(&bus->conf_mutex);
@@ -620 +639 @@
                         ddf_msg(LVL_DEBUG, "Adding new function %s.",
                             ddf_fun_get_name(fun->fnode));
-                        
+
                         pci_fun_create_match_ids(fun);
                         
@@ -688 +707 @@
         
         
-        assert(hw_resources.count > 1);
-        assert(hw_resources.resources[0].type == IO_RANGE);
-        assert(hw_resources.resources[0].res.io_range.size >= 4);
-        
-        assert(hw_resources.resources[1].type == IO_RANGE);
-        assert(hw_resources.resources[1].res.io_range.size >= 4);
-        
-        ddf_msg(LVL_DEBUG, "conf_addr = %" PRIx64 ".",
-            hw_resources.resources[0].res.io_range.address);
-        ddf_msg(LVL_DEBUG, "data_addr = %" PRIx64 ".",
-            hw_resources.resources[1].res.io_range.address);
-        
-        if (pio_enable_resource(&bus->pio_win, &hw_resources.resources[0],
-            (void **) &bus->conf_addr_reg)) {
-                ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
-                rc = EADDRNOTAVAIL;
-                goto fail;
-        }
-        if (pio_enable_resource(&bus->pio_win, &hw_resources.resources[1],
-            (void **) &bus->conf_data_reg)) {
-                ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
-                rc = EADDRNOTAVAIL;
-                goto fail;
+        assert(hw_resources.count >= 1);
+
+        if (hw_resources.count == 1) {
+                assert(hw_resources.resources[0].type == MEM_RANGE);
+
+                ddf_msg(LVL_DEBUG, "conf_addr_space = %" PRIx64 ".",
+                    hw_resources.resources[0].res.mem_range.address);
+
+                if (pio_enable_resource(&bus->pio_win,
+                    &hw_resources.resources[0],
+                    (void **) &bus->conf_space)) {
+                        ddf_msg(LVL_ERROR,
+                            "Failed to map configuration space.");
+                        rc = EADDRNOTAVAIL;
+                        goto fail;
+                }
+                
+        } else {
+                assert(hw_resources.resources[0].type == IO_RANGE);
+                assert(hw_resources.resources[0].res.io_range.size >= 4);
+        
+                assert(hw_resources.resources[1].type == IO_RANGE);
+                assert(hw_resources.resources[1].res.io_range.size >= 4);
+        
+                ddf_msg(LVL_DEBUG, "conf_addr = %" PRIx64 ".",
+                    hw_resources.resources[0].res.io_range.address);
+                ddf_msg(LVL_DEBUG, "data_addr = %" PRIx64 ".",
+                    hw_resources.resources[1].res.io_range.address);
+        
+                if (pio_enable_resource(&bus->pio_win,
+                    &hw_resources.resources[0],
+                    (void **) &bus->conf_addr_reg)) {
+                        ddf_msg(LVL_ERROR,
+                            "Failed to enable configuration ports.");
+                        rc = EADDRNOTAVAIL;
+                        goto fail;
+                }
+                if (pio_enable_resource(&bus->pio_win,
+                    &hw_resources.resources[1],
+                    (void **) &bus->conf_data_reg)) {
+                        ddf_msg(LVL_ERROR,
+                            "Failed to enable configuration ports.");
+                        rc = EADDRNOTAVAIL;
+                        goto fail;
+                }
         }
         

uspace/drv/bus/pci/pciintel/pci.h

@@ -47 +47 @@
         ioport32_t *conf_addr_reg;
         ioport32_t *conf_data_reg;
+        ioport32_t *conf_space;
         pio_window_t pio_win;
         fibril_mutex_t conf_mutex;