Changes in kernel/arch/ia64/src/start.S [acee917:93d66ef] in mainline
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kernel/arch/ia64/src/start.S
racee917 r93d66ef 32 32 #include <mm/asid.h> 33 33 34 #define RR_MASK (0xFFFFFFFF00000002)35 #define RID_SHIFT 36 #define PS_SHIFT 37 38 #define KERNEL_TRANSLATION_I 39 #define KERNEL_TRANSLATION_D 40 #define KERNEL_TRANSLATION_VIO 41 #define KERNEL_TRANSLATION_IO 0x00100FFFFC00067142 #define KERNEL_TRANSLATION_FW 0x00100000F000067134 #define RR_MASK (0xFFFFFFFF00000002) 35 #define RID_SHIFT 8 36 #define PS_SHIFT 2 37 38 #define KERNEL_TRANSLATION_I 0x0010000000000661 39 #define KERNEL_TRANSLATION_D 0x0010000000000661 40 #define KERNEL_TRANSLATION_VIO 0x0010000000000671 41 #define KERNEL_TRANSLATION_IO 0x00100FFFFC000671 42 #define KERNEL_TRANSLATION_FW 0x00100000F0000671 43 43 44 44 .section K_TEXT_START, "ax" … … 49 49 kernel_image_start: 50 50 .auto 51 51 52 52 #ifdef CONFIG_SMP 53 53 # Identify self(CPU) in OS structures by ID / EID 54 54 55 55 mov r9 = cr64 56 56 mov r10 = 1 … … 62 62 st1 [r8] = r10 63 63 #endif 64 64 65 65 mov psr.l = r0 66 66 srlz.i 67 67 srlz.d 68 68 69 69 # Fill TR.i and TR.d using Region Register #VRN_KERNEL 70 70 71 71 movl r8 = (VRN_KERNEL << VRN_SHIFT) 72 72 mov r9 = rr[r8] 73 73 74 74 movl r10 = (RR_MASK) 75 75 and r9 = r10, r9 76 76 movl r10 = ((RID_KERNEL << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT)) 77 or 78 77 or r9 = r10, r9 78 79 79 mov rr[r8] = r9 80 80 81 81 movl r8 = (VRN_KERNEL << VRN_SHIFT) 82 82 mov cr.ifa = r8 83 83 84 84 mov r11 = cr.itir 85 85 movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT) 86 86 or r10 = r10, r11 87 87 mov cr.itir = r10 88 88 89 89 movl r10 = (KERNEL_TRANSLATION_I) 90 90 itr.i itr[r0] = r10 91 91 movl r10 = (KERNEL_TRANSLATION_D) 92 92 itr.d dtr[r0] = r10 93 93 94 94 movl r7 = 1 95 95 movl r8 = (VRN_KERNEL << VRN_SHIFT) | VIO_OFFSET … … 97 97 movl r10 = (KERNEL_TRANSLATION_VIO) 98 98 itr.d dtr[r7] = r10 99 99 100 100 mov r11 = cr.itir 101 101 movl r10 = ~0xfc … … 104 104 or r10 = r10, r11 105 105 mov cr.itir = r10 106 106 107 107 movl r7 = 2 108 108 movl r8 = (VRN_KERNEL << VRN_SHIFT) | IO_OFFSET … … 110 110 movl r10 = (KERNEL_TRANSLATION_IO) 111 111 itr.d dtr[r7] = r10 112 113 # Setup mapping for fi mware arrea (also SAPIC)114 112 113 # Setup mapping for firmware area (also SAPIC) 114 115 115 mov r11 = cr.itir 116 116 movl r10 = ~0xfc … … 119 119 or r10 = r10, r11 120 120 mov cr.itir = r10 121 121 122 122 movl r7 = 3 123 123 movl r8 = (VRN_KERNEL << VRN_SHIFT) | FW_OFFSET … … 125 125 movl r10 = (KERNEL_TRANSLATION_FW) 126 126 itr.d dtr[r7] = r10 127 127 128 # Initialize DSR 129 130 movl r10 = (DCR_DP_MASK | DCR_DK_MASK | DCR_DX_MASK | DCR_DR_MASK | DCR_DA_MASK | DCR_DD_MASK | DCR_LC_MASK) 131 mov r9 = cr.dcr 132 or r10 = r10, r9 133 mov cr.dcr = r10 134 128 135 # Initialize PSR 129 136 130 137 movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK) /* Enable paging */ 131 138 mov r9 = psr 132 139 133 140 or r10 = r10, r9 134 141 mov cr.ipsr = r10 … … 138 145 srlz.d 139 146 srlz.i 140 147 141 148 .explicit 142 149 143 150 /* 144 151 * Return From Interrupt is the only way to … … 147 154 rfi ;; 148 155 149 150 156 .global paging_start 151 157 paging_start: 152 158 153 159 /* 154 160 * Now we are paging. 155 161 */ 156 162 157 163 # Switch to register bank 1 158 164 bsw.1 159 165 160 166 #ifdef CONFIG_SMP 161 167 # Am I BSP or AP? … … 164 170 cmp.eq p3, p2 = r20, r0 ;; 165 171 #else 166 cmp.eq p3, p2 = r0, r0 ;; 167 #endif 172 cmp.eq p3, p2 = r0, r0 ;; /* you are BSP */ 173 #endif /* CONFIG_SMP */ 168 174 169 175 # Initialize register stack … … 172 178 mov ar.bspstore = r8 173 179 loadrs 174 180 175 181 # Initialize memory stack to some sane value 176 182 movl r12 = stack0 ;; 177 add r12 = -16, r12 178 183 add r12 = -16, r12 /* allocate a scratch area on the stack */ 184 179 185 # Initialize gp (Global Pointer) register 180 movl r20 = (VRN_KERNEL << VRN_SHIFT) ;;181 or r20 = r20, r1;;186 movl r20 = (VRN_KERNEL << VRN_SHIFT) ;; 187 or r20 = r20, r1 ;; 182 188 movl r1 = _hardcoded_load_address 183 189 … … 192 198 (p3) addl r19 = @gprel(hardcoded_load_address), gp 193 199 (p3) addl r21 = @gprel(bootinfo), gp 194 ;;200 ;; 195 201 (p3) st8 [r17] = r14 196 202 (p3) st8 [r18] = r15 197 203 (p3) st8 [r19] = r16 198 204 (p3) st8 [r21] = r20 199 205 200 206 ssm (1 << 19) ;; /* Disable f32 - f127 */ 201 207 srlz.i 202 208 srlz.d ;; 203 209 204 210 #ifdef CONFIG_SMP 205 211 (p2) movl r18 = main_ap ;; 206 (p2) 212 (p2) mov b1 = r18 ;; 207 213 (p2) br.call.sptk.many b0 = b1 208 214 209 215 # Mark that BSP is on 216 210 217 mov r20 = 1 ;; 211 218 movl r21 = bsp_started ;; 212 219 st8 [r21] = r20 ;; 213 220 #endif 214 221 215 222 br.call.sptk.many b0 = arch_pre_main 216 223 217 224 movl r18 = main_bsp ;; 218 225 mov b1 = r18 ;; … … 227 234 kernel_image_ap_start: 228 235 .auto 229 236 230 237 # Identify self(CPU) in OS structures by ID / EID 231 238 232 239 mov r9 = cr64 233 240 mov r10 = 1 … … 240 247 241 248 # Wait for wakeup synchro signal (#3 in cpu_by_id_eid_list) 242 249 243 250 kernel_image_ap_start_loop: 244 251 movl r11 = kernel_image_ap_start_loop 245 252 and r11 = r11, r12 246 mov b1 = r11 247 248 ld1 r20 = [r8] ;;249 movl r21 = 3 ;;250 cmp.eq p2, p3 = r20, r21 ;;253 mov b1 = r11 254 255 ld1 r20 = [r8] 256 movl r21 = 3 257 cmp.eq p2, p3 = r20, r21 251 258 (p3) br.call.sptk.many b0 = b1 252 259 253 260 movl r11 = kernel_image_start 254 261 and r11 = r11, r12 255 mov b1 = r11 262 mov b1 = r11 256 263 br.call.sptk.many b0 = b1 257 264 … … 259 266 .global bsp_started 260 267 bsp_started: 261 .space 8268 .space 8 262 269 263 270 .align 4096 264 271 .global cpu_by_id_eid_list 265 272 cpu_by_id_eid_list: 266 .space 65536267 268 #endif 273 .space 65536 274 275 #endif /* CONFIG_SMP */
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