Changes in kernel/arch/arm32/src/cpu/cpu.c [c8a5c8c:93d8022] in mainline

File:

• kernel/arch/arm32/src/cpu/cpu.c (modified) (12 diffs)

kernel/arch/arm32/src/cpu/cpu.c

@@ -41 +41 @@
 #include <print.h>
 
+#ifdef CONFIG_FPU
+#include <arch/fpu_context.h>
+#endif
+
 static inline unsigned log2(unsigned val)
 {
@@ -60 +64 @@
 static const char * implementer(unsigned id)
 {
-        switch (id)
-        {
+        switch (id) {
         case 0x41: return "ARM Limited";
         case 0x44: return "Digital Equipment Corporation";
@@ -127 +130 @@
 {
         uint32_t control_reg = SCTLR_read();
-        
+
+        dcache_invalidate();
+        read_barrier();
+
         /* Turn off tex remap, RAZ/WI prior to armv7 */
         control_reg &= ~SCTLR_TEX_REMAP_EN_FLAG;
@@ -157 +163 @@
 #endif
 #ifdef PROCESSOR_ARCH_armv7_a
-         /* ICache coherency is elaborate on in barrier.h.
+         /* ICache coherency is elaborated on in barrier.h.
           * VIPT and PIPT caches need maintenance only on code modify,
           * so it should be safe for general use.
@@ -166 +172 @@
                 control_reg |=
                     SCTLR_INST_CACHE_EN_FLAG | SCTLR_BRANCH_PREDICT_EN_FLAG;
+        } else {
+                control_reg &=
+                    ~(SCTLR_INST_CACHE_EN_FLAG | SCTLR_BRANCH_PREDICT_EN_FLAG);
         }
 #endif
@@ -204 +213 @@
 #ifdef PROCESSOR_ARCH_armv7_a
         CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
-        const unsigned ls_log = 2 +
-            ((CCSIDR_read() >> CCSIDR_LINESIZE_SHIFT) & CCSIDR_LINESIZE_MASK);
-        return ls_log + 2; //return log2(bytes)
+        const uint32_t ccsidr = CCSIDR_read();
+        return CCSIDR_LINESIZE_LOG(ccsidr);
 #endif
         return 0;
@@ -217 +225 @@
 #ifdef PROCESSOR_ARCH_armv7_a
         CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
-        const unsigned ways = 1 +
-            ((CCSIDR_read() >> CCSIDR_ASSOC_SHIFT) & CCSIDR_ASSOC_MASK);
-        return ways;
+        const uint32_t ccsidr = CCSIDR_read();
+        return CCSIDR_WAYS(ccsidr);
 #endif
         return 0;
@@ -229 +236 @@
 #ifdef PROCESSOR_ARCH_armv7_a
         CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
-        const unsigned sets = 1 +
-            ((CCSIDR_read() >> CCSIDR_NUMSETS_SHIFT) & CCSIDR_NUMSETS_MASK);
-        return sets;
+        const uint32_t ccsidr = CCSIDR_read();
+        return CCSIDR_SETS(ccsidr);
 #endif
         return 0;
@@ -241 +247 @@
 #ifdef PROCESSOR_ARCH_armv7_a
         const uint32_t val = CLIDR_read();
-        for (unsigned i = 1; i <= 7; ++i) {
+        for (unsigned i = 0; i < 8; ++i) {
                 const unsigned ctype = CLIDR_CACHE(i, val);
                 switch (ctype) {
@@ -280 +286 @@
                 const unsigned ways = dcache_ways(i);
                 const unsigned sets = dcache_sets(i);
-                const unsigned way_shift =  31 - log2(ways);
+                const unsigned way_shift = 32 - log2(ways);
                 const unsigned set_shift = dcache_linesize_log(i);
                 dcache_clean_manual(i, false, ways, sets, way_shift, set_shift);
@@ -293 +299 @@
                 const unsigned ways = dcache_ways(i);
                 const unsigned sets = dcache_sets(i);
-                const unsigned way_shift =  31 - log2(ways);
+                const unsigned way_shift = 32 - log2(ways);
                 const unsigned set_shift = dcache_linesize_log(i);
                 dcache_clean_manual(i, true, ways, sets, way_shift, set_shift);
@@ -319 +325 @@
 void icache_invalidate(void)
 {
+#if defined(PROCESSOR_ARCH_armv7_a)
         ICIALLU_write(0);
+#else
+        ICIALL_write(0);
+#endif
+}
+
+#if !defined(PROCESSOR_ARCH_armv7_a)
+static bool cache_is_unified(void)
+{
+        if (MIDR_read() != CTR_read()) {
+                /* We have the CTR register */
+                return (CTR_read() & CTR_SEP_FLAG) != CTR_SEP_FLAG;
+        } else {
+                panic("Unknown cache type");
+        }
+}
+#endif
+
+void dcache_invalidate(void)
+{
+#if defined(PROCESSOR_ARCH_armv7_a)
+        dcache_flush_invalidate();
+#else
+        if (cache_is_unified())
+                CIALL_write(0);
+        else
+                DCIALL_write(0);
+#endif
+}
+
+void dcache_clean_mva_pou(uintptr_t mva)
+{
+#if defined(PROCESSOR_ARCH_armv7_a)
+        DCCMVAU_write(mva);
+#else
+        if (cache_is_unified())
+                CCMVA_write(mva);
+        else
+                DCCMVA_write(mva);
+#endif
 }