Changeset 93d8022 in mainline for uspace/app/trace/trace.c

Timestamp:

2015-10-26T21:12:57Z (9 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

5783d10

Parents:

1a2a6e7

Message:

ARM cache handling fixes

• boot: Use the normal outer and inner WBWA attribute also for ARMv6
• kernel: Fix comment in page_armv6.h:set_pt_level0_flags(). TEX=5, C=0, B=1 encodes outer and inner WBWA normal memory.
• Treat all normal memory as non shareable also on ARMv6.
• Make sure D$ is invalidated in cpu_arch_init() before it is enabled.
• For non-cacheable ARMv6+ memory, use device memory type instead of strongly-ordered.
• For ARMv5-, use either cached/buffered (CB=0b11) or uncached/unbuffered (CB=0b00).

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