Changes in / [0d57c3e:96e01fbc] in mainline


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Files:
17 added
30 edited

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Added
Removed

  • HelenOS.config

    r0d57c3e r96e01fbc  
    6565@ "testarm" GXEmul Testarm
    6666@ "integratorcp" Integratorcp
     67@ "beagleboardxm" BeogleBoard-xM
    6768! [PLATFORM=arm32] MACHINE (choice)
    6869
    … …  
    8687! [PLATFORM=sparc64&MACHINE=generic] PROCESSOR (choice)
    8788
     89% CPU type
     90@ "armv4" ARMv4
     91! [PLATFORM=arm32&(MACHINE=gta02|MACHINE=gxemul)] PROCESSOR (choice)
     92
     93% CPU type
     94@ "armv5" ARMv5
     95! [PLATFORM=arm32&MACHINE=integratorcp] PROCESSOR (choice)
     96
     97% CPU type
     98@ "armv7_a" ARMv7-A
     99! [PLATFORM=arm32&MACHINE=beagleboardxm] PROCESSOR (choice)
     100
     101
    88102% RAM disk format
    89103@ "tmpfs" TMPFS image
    … …  
    406420% Output device class
    407421@ "generic" Monitor or serial line
    408 ! [PLATFORM=arm32&(MACHINE=gta02|MACHINE=integratorcp)] CONFIG_HID_OUT (choice)
     422! [PLATFORM=arm32&(MACHINE=gta02|MACHINE=integratorcp|MACHINE=beagleboardxm)] CONFIG_HID_OUT (choice)
    409423
    410424% Output device class
    … …  
    463477! [PLATFORM=arm32&MACHINE=gta02] CONFIG_S3C24XX_IRQC (y)
    464478
     479% Support for TI AMDM37X on-chip UART
     480! [(CONFIG_HID_OUT=generic|CONFIG_HID_OUT=serial)&PLATFORM=arm32&MACHINE=beagleboardxm] CONFIG_AMDM37X_UART (y/n)
     481
    465482% Support for i8042 controller
    466483! [CONFIG_PC_KBD=y] CONFIG_I8042 (y)
    … …  
    482499
    483500% Serial line input module
    484 ! [CONFIG_DSRLNIN=y|(PLATFORM=arm32&MACHINE=gta02)|(PLATFORM=ia64&MACHINE=i460GX&CONFIG_NS16550=y)|(PLATFORM=ia64&MACHINE=ski)|(PLATFORM=sparc64&PROCESSOR=sun4v)] CONFIG_SRLN (y)
     501! [CONFIG_DSRLNIN=y|(PLATFORM=arm32&MACHINE=gta02)|(PLATFORM=arm32&MACHINE=beagleboardxm)|(PLATFORM=ia64&MACHINE=i460GX&CONFIG_NS16550=y)|(PLATFORM=ia64&MACHINE=ski)|(PLATFORM=sparc64&PROCESSOR=sun4v)] CONFIG_SRLN (y)
    485502
    486503% EGA support
    … …  
    518535@ "1920x1080"
    519536@ "1920x1200"
    520 ! [(PLATFORM=ia32|PLATFORM=amd64)&CONFIG_HID_OUT!=none&CONFIG_FB=y] CONFIG_BFB_MODE (choice)
     537! [(PLATFORM=ia32|PLATFORM=amd64|MACHINE=beagleboardxm)&CONFIG_HID_OUT!=none&CONFIG_FB=y] CONFIG_BFB_MODE (choice)
    521538
    522539% Default framebuffer depth
    … …  
    524541@ "16"
    525542@ "24"
    526 ! [(PLATFORM=ia32|PLATFORM=amd64)&CONFIG_HID_OUT!=none&CONFIG_FB=y] CONFIG_BFB_BPP (choice)
     543! [(PLATFORM=ia32|PLATFORM=amd64|MACHINE=beagleboardxm)&CONFIG_HID_OUT!=none&CONFIG_FB=y] CONFIG_BFB_BPP (choice)
    527544
    528545% Start AP processors by the loader

  • boot/Makefile.uboot

    r0d57c3e r96e01fbc  
    4040
    4141$(POST_OUTPUT): $(BIN_OUTPUT)
    42         $(MKUIMAGE) -name "$(IMAGE_NAME)" -laddr 0x30008000 -saddr 0x30008000 $< $@
     42        $(MKUIMAGE) -name "$(IMAGE_NAME)" -laddr $(LADDR) -saddr $(SADDR) $< $@
    4343
    4444clean:

  • boot/arch/arm32/Makefile.inc

    r0d57c3e r96e01fbc  
    3030        BOOT_OUTPUT = image.boot
    3131        POST_OUTPUT = $(ROOT_PATH)/uImage.bin
     32        LADDR = 0x30008000
     33        SADDR = 0x30008000
     34        POSTBUILD = Makefile.uboot
     35endif
     36
     37ifeq ($(MACHINE), beagleboardxm)
     38        BOOT_OUTPUT = image.boot
     39        POST_OUTPUT = $(ROOT_PATH)/uImage.bin
     40        LADDR = 0x80000000
     41        SADDR = 0x80000000
    3242        POSTBUILD = Makefile.uboot
    3343endif
    … …  
    3949BITS = 32
    4050ENDIANESS = LE
    41 EXTRA_CFLAGS = -march=armv4
     51EXTRA_CFLAGS = -march=$(subst _,-,$(PROCESSOR))
    4252
     53ifeq ($(MACHINE), gta02)
    4354RD_SRVS_ESSENTIAL += \
    4455        $(USPACE_PATH)/srv/hid/s3c24xx_ts/s3c24xx_ts \
    4556        $(USPACE_PATH)/srv/hw/char/s3c24xx_uart/s3c24xx_uart
     57endif
    4658
     59ifeq ($(MACHINE), gxemul)
    4760RD_SRVS_NON_ESSENTIAL += \
    4861        $(USPACE_PATH)/srv/bd/gxe_bd/gxe_bd
     62endif
     63
     64RD_DRVS += \
     65        infrastructure/rootamdm37x \
     66        bus/usb/ehci \
     67        bus/usb/ohci \
     68        bus/usb/usbflbk \
     69        bus/usb/usbhub \
     70        bus/usb/usbhid \
     71        bus/usb/usbmast \
     72        bus/usb/usbmid
    4973
    5074SOURCES = \

  • boot/arch/arm32/include/arch.h

    r0d57c3e r96e01fbc  
    4242#ifdef MACHINE_gta02
    4343#define BOOT_BASE       0x30008000
     44#elif defined MACHINE_beagleboardxm
     45#define BOOT_BASE       0x80000000
    4446#else
    4547#define BOOT_BASE       0x00000000
    … …  
    4850#define BOOT_OFFSET     (BOOT_BASE + 0xa00000)
    4951
     52#ifdef MACHINE_beagleboardxm
     53        #define PA_OFFSET 0
     54#else
     55        #define PA_OFFSET 0x80000000
     56#endif
     57
    5058#ifndef __ASM__
    51         #define PA2KA(addr)  (((uintptr_t) (addr)) + 0x80000000)
     59        #define PA2KA(addr)  (((uintptr_t) (addr)) + PA_OFFSET)
    5260#else
    53         #define PA2KA(addr)  ((addr) + 0x80000000)
     61        #define PA2KA(addr)  ((addr) + PA_OFFSET)
    5462#endif
     63
    5564
    5665#endif

  • boot/arch/arm32/include/main.h

    r0d57c3e r96e01fbc  
    4040/** Address where characters to be printed are expected. */
    4141
     42
     43/** BeagleBoard-xM UART register address
     44 *
     45 * This is UART3 of AM/DM37x CPU
     46 */
     47#define BBXM_SCONS_THR          0x49020000
     48#define BBXM_SCONS_SSR          0x49020044
     49
     50/* Check this bit before writing (tx fifo full) */
     51#define BBXM_THR_FULL           0x00000001
     52
     53
    4254/** GTA02 serial console UART register addresses.
    4355 *

  • boot/arch/arm32/include/mm.h

    r0d57c3e r96e01fbc  
    5858        unsigned int bufferable : 1;
    5959        unsigned int cacheable : 1;
    60         unsigned int impl_specific : 1;
     60        unsigned int xn : 1;
    6161        unsigned int domain : 4;
    6262        unsigned int should_be_zero_1 : 1;
    63         unsigned int access_permission : 2;
    64         unsigned int should_be_zero_2 : 8;
     63        unsigned int access_permission_0 : 2;
     64        unsigned int tex : 3;
     65        unsigned int access_permission_1 : 2;
     66        unsigned int non_global : 1;
     67        unsigned int should_be_zero_2 : 1;
     68        unsigned int non_secure : 1;
    6569        unsigned int section_base_addr : 12;
    6670} __attribute__((packed)) pte_level0_section_t;

  • boot/arch/arm32/src/mm.c

    r0d57c3e r96e01fbc  
    5454{
    5555        pte->descriptor_type = PTE_DESCRIPTOR_SECTION;
    56         pte->bufferable = 0;
     56        pte->bufferable = 1;
    5757        pte->cacheable = 0;
    58         pte->impl_specific = 0;
     58        pte->xn = 0;
    5959        pte->domain = 0;
    6060        pte->should_be_zero_1 = 0;
    61         pte->access_permission = PTE_AP_USER_NO_KERNEL_RW;
     61        pte->access_permission_0 = PTE_AP_USER_NO_KERNEL_RW;
     62        pte->tex = 0;
     63        pte->access_permission_1 = 0;
     64        pte->non_global = 0;
    6265        pte->should_be_zero_2 = 0;
     66        pte->non_secure = 0;
    6367        pte->section_base_addr = frame;
    6468}
    … …  
    6771static void init_boot_pt(void)
    6872{
    69         pfn_t split_page = 0x800;
    70        
     73        const pfn_t split_page = PTL0_ENTRIES;
    7174        /* Create 1:1 virtual-physical mapping (in lower 2 GB). */
    7275        pfn_t page;
    … …  
    7881         * (upper 2 GB), physical addresses start from 0.
    7982         */
     83        /* BeagleBoard-xM (MD37x) memory starts at 2GB border,
     84         * thus mapping only lower 2GB is not not enough.
     85         * Map entire AS 1:1 instead and hope it works. */
    8086        for (page = split_page; page < PTL0_ENTRIES; page++)
     87#ifndef MACHINE_beagleboardxm
    8188                init_ptl0_section(&boot_pt[page], page - split_page);
     89#else
     90                init_ptl0_section(&boot_pt[page], page);
     91#endif
    8292       
    8393        asm volatile (
    … …  
    95105                /* Behave as a client of domains */
    96106                "ldr r0, =0x55555555\n"
    97                 "mcr p15, 0, r0, c3, c0, 0\n" 
     107                "mcr p15, 0, r0, c3, c0, 0\n"
    98108               
     109#ifdef PROCESSOR_armv7_a
     110                /* Read Auxiliary control register */
     111                "mrc p15, 0, r0, c1, c0, 1\n"
     112                /* Mask to enable L2 cache */
     113                "ldr r1, =0x00000002\n"
     114                "orr r0, r0, r1\n"
     115                /* Store Auxiliary control register */
     116                "mrc p15, 0, r0, c1, c0, 1\n"
     117#endif
    99118                /* Current settings */
    100119                "mrc p15, 0, r0, c1, c0, 0\n"
    101120               
     121#ifdef PROCESSOR_armv7_a
     122                /* Mask to enable paging, caching */
     123                "ldr r1, =0x00000005\n"
     124#else
    102125                /* Mask to enable paging */
    103126                "ldr r1, =0x00000001\n"
     127#endif
    104128                "orr r0, r0, r1\n"
    105129               

  • boot/arch/arm32/src/putchar.c

    r0d57c3e r96e01fbc  
    4040#include <putchar.h>
    4141#include <str.h>
     42
     43#ifdef MACHINE_beagleboardxm
     44
     45/** Send a byte to the amdm37x serial console.
     46 *
     47 * @param byte          Byte to send.
     48 */
     49static void scons_sendb_bbxm(uint8_t byte)
     50{
     51        volatile uint32_t *thr =
     52            (volatile uint32_t *)BBXM_SCONS_THR;
     53        volatile uint32_t *ssr =
     54            (volatile uint32_t *)BBXM_SCONS_SSR;
     55
     56        /* Wait until transmitter is empty. */
     57        while ((*ssr & BBXM_THR_FULL) == 1) ;
     58
     59        /* Transmit byte. */
     60        *thr = (uint32_t) byte;
     61}
     62
     63#endif
    4264
    4365#ifdef MACHINE_gta02
    … …  
    97119static void scons_sendb(uint8_t byte)
    98120{
     121#ifdef MACHINE_beagleboardxm
     122        scons_sendb_bbxm(byte);
     123#endif
    99124#ifdef MACHINE_gta02
    100125        scons_sendb_gta02(byte);

  • kernel/arch/arm32/Makefile.inc

    r0d57c3e r96e01fbc  
    3333ATSIGN = %
    3434
    35 GCC_CFLAGS += -march=armv4
     35GCC_CFLAGS += -march=$(subst _,-,$(PROCESSOR))
    3636
    3737BITS = 32
    … …  
    7474endif
    7575
     76ifeq ($(MACHINE),beagleboardxm)
     77        ARCH_SOURCES += arch/$(KARCH)/src/mach/beagleboardxm/beagleboardxm.c
     78endif
     79
    7680ifeq ($(CONFIG_PL050),y)
    7781        ARCH_SOURCES += genarch/src/drivers/pl050/pl050.c

  • kernel/arch/arm32/_link.ld.in

    r0d57c3e r96e01fbc  
    99#ifdef MACHINE_gta02
    1010#define KERNEL_LOAD_ADDRESS 0xb0a08000
     11#elif defined MACHINE_beagleboardxm
     12#define KERNEL_LOAD_ADDRESS 0x80a00000
    1113#else
    1214#define KERNEL_LOAD_ADDRESS 0x80a00000

  • kernel/arch/arm32/include/asm.h

    r0d57c3e r96e01fbc  
    4343#include <trace.h>
    4444
    45 /** No such instruction on ARM to sleep CPU. */
     45/** No such instruction on old ARM to sleep CPU.
     46 *
     47 * ARMv7 introduced wait for event and wait for interrupt (wfe/wfi).
     48 */
    4649NO_TRACE static inline void cpu_sleep(void)
    4750{
     51#ifdef PROCESSOR_armv7_a
     52        asm volatile ( "wfe" :: );
     53#endif
    4854}
    4955

  • kernel/arch/arm32/include/cpu.h

    r0d57c3e r96e01fbc  
    4141
    4242
    43 /** Struct representing ARM CPU identifiaction. */
     43/** Struct representing ARM CPU identification. */
    4444typedef struct {
    4545        /** Implementator (vendor) number. */

  • kernel/arch/arm32/include/machine_func.h

    r0d57c3e r96e01fbc  
    108108extern size_t machine_get_irq_count(void);
    109109
     110extern const char * machine_get_platform_name(void);
     111
    110112#endif
    111113

  • kernel/arch/arm32/include/mm/frame.h

    r0d57c3e r96e01fbc  
    4848#ifdef MACHINE_gta02
    4949#define BOOT_PAGE_TABLE_ADDRESS  0x30010000
     50#elif defined MACHINE_beagleboardxm
     51#define BOOT_PAGE_TABLE_ADDRESS  0x80008000
    5052#else
    5153#define BOOT_PAGE_TABLE_ADDRESS  0x00008000
    … …  
    5759#ifdef MACHINE_gta02
    5860#define PHYSMEM_START_ADDR      0x30008000
     61#elif defined MACHINE_beagleboardxm
     62#define PHYSMEM_START_ADDR      0x80000000
    5963#else
    6064#define PHYSMEM_START_ADDR      0x00000000

  • kernel/arch/arm32/include/mm/page.h

    r0d57c3e r96e01fbc  
    4646#define PAGE_SIZE       FRAME_SIZE
    4747
     48#ifdef MACHINE_beagleboardxm
     49#ifndef __ASM__
     50#       define KA2PA(x) ((uintptr_t) (x))
     51#       define PA2KA(x) ((uintptr_t) (x))
     52#else
     53#       define KA2PA(x) (x)
     54#       define PA2KA(x) (x)
     55#endif
     56#else
    4857#ifndef __ASM__
    4958#       define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
    … …  
    5362#       define PA2KA(x) ((x) + 0x80000000)
    5463#endif
     64#endif
    5565
    5666/* Number of entries in each level. */
    57 #define PTL0_ENTRIES_ARCH       (1 << 12)       /* 4096 */
    58 #define PTL1_ENTRIES_ARCH       0
    59 #define PTL2_ENTRIES_ARCH       0
     67#define PTL0_ENTRIES_ARCH       (1 << 12)       /* 4096 */
     68#define PTL1_ENTRIES_ARCH       0
     69#define PTL2_ENTRIES_ARCH       0
    6070/* coarse page tables used (256 * 4 = 1KB per page) */
    61 #define PTL3_ENTRIES_ARCH       (1 << 8)        /* 256 */
     71#define PTL3_ENTRIES_ARCH       (1 << 8)        /* 256 */
    6272
    6373/* Page table sizes for each level. */
    64 #define PTL0_SIZE_ARCH          FOUR_FRAMES
    65 #define PTL1_SIZE_ARCH          0
    66 #define PTL2_SIZE_ARCH          0
    67 #define PTL3_SIZE_ARCH          ONE_FRAME
     74#define PTL0_SIZE_ARCH          FOUR_FRAMES
     75#define PTL1_SIZE_ARCH          0
     76#define PTL2_SIZE_ARCH          0
     77#define PTL3_SIZE_ARCH          ONE_FRAME
    6878
    6979/* Macros calculating indices into page tables for each level. */
    70 #define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 20) & 0xfff)
    71 #define PTL1_INDEX_ARCH(vaddr)  0
    72 #define PTL2_INDEX_ARCH(vaddr)  0
    73 #define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x0ff)
     80#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 20) & 0xfff)
     81#define PTL1_INDEX_ARCH(vaddr)  0
     82#define PTL2_INDEX_ARCH(vaddr)  0
     83#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x0ff)
    7484
    7585/* Get PTE address accessors for each level. */
    7686#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
    77         ((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10))
     87        ((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10))
    7888#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
    79         (ptl1)
     89        (ptl1)
    8090#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
    81         (ptl2)
     91        (ptl2)
    8292#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
    83         ((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12))
     93        ((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12))
    8494
    8595/* Set PTE address accessors for each level. */
    8696#define SET_PTL0_ADDRESS_ARCH(ptl0) \
    87         (set_ptl0_addr((pte_t *) (ptl0)))
     97        (set_ptl0_addr((pte_t *) (ptl0)))
    8898#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
    89         (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10)
     99        (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10)
    90100#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
    91101#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
    92102#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
    93         (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12)
     103        (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12)
    94104
    95105/* Get PTE flags accessors for each level. */
    96106#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
    97         get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i))
     107        get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i))
    98108#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
    99         PAGE_PRESENT
     109        PAGE_PRESENT
    100110#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
    101         PAGE_PRESENT
     111        PAGE_PRESENT
    102112#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
    103         get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i))
     113        get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i))
    104114
    105115/* Set PTE flags accessors for each level. */
    106116#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
    107         set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x))
     117        set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x))
    108118#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
    109119#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
    … …  
    119129        set_pt_level1_present((pte_t *) (ptl3), (size_t) (i))
    120130
    121 /* Macros for querying the last-level PTE entries. */
    122 #define PTE_VALID_ARCH(pte) \
    123         (*((uint32_t *) (pte)) != 0)
    124 #define PTE_PRESENT_ARCH(pte) \
    125         (((pte_t *) (pte))->l0.descriptor_type != 0)
    126 #define PTE_GET_FRAME_ARCH(pte) \
    127         (((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH)
    128 #define PTE_WRITABLE_ARCH(pte) \
    129         (((pte_t *) (pte))->l1.access_permission_0 == PTE_AP_USER_RW_KERNEL_RW)
    130 #define PTE_EXECUTABLE_ARCH(pte) \
    131         1
    132 
    133 #ifndef __ASM__
    134 
    135 /** Level 0 page table entry. */
    136 typedef struct {
    137         /* 0b01 for coarse tables, see below for details */
    138         unsigned descriptor_type : 2;
    139         unsigned impl_specific : 3;
    140         unsigned domain : 4;
    141         unsigned should_be_zero : 1;
    142 
    143         /* Pointer to the coarse 2nd level page table (holding entries for small
    144          * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page
    145          * tables that may hold even tiny pages (1KB) but they are bigger (4KB
    146          * per table in comparison with 1KB per the coarse table)
    147          */
    148         unsigned coarse_table_addr : 22;
    149 } ATTRIBUTE_PACKED pte_level0_t;
    150 
    151 /** Level 1 page table entry (small (4KB) pages used). */
    152 typedef struct {
    153 
    154         /* 0b10 for small pages */
    155         unsigned descriptor_type : 2;
    156         unsigned bufferable : 1;
    157         unsigned cacheable : 1;
    158 
    159         /* access permissions for each of 4 subparts of a page
    160          * (for each 1KB when small pages used */
    161         unsigned access_permission_0 : 2;
    162         unsigned access_permission_1 : 2;
    163         unsigned access_permission_2 : 2;
    164         unsigned access_permission_3 : 2;
    165         unsigned frame_base_addr : 20;
    166 } ATTRIBUTE_PACKED pte_level1_t;
    167 
    168 typedef union {
    169         pte_level0_t l0;
    170         pte_level1_t l1;
    171 } pte_t;
    172 
    173 /* Level 1 page tables access permissions */
    174 
    175 /** User mode: no access, privileged mode: no access. */
    176 #define PTE_AP_USER_NO_KERNEL_NO        0
    177 
    178 /** User mode: no access, privileged mode: read/write. */
    179 #define PTE_AP_USER_NO_KERNEL_RW        1
    180 
    181 /** User mode: read only, privileged mode: read/write. */
    182 #define PTE_AP_USER_RO_KERNEL_RW        2
    183 
    184 /** User mode: read/write, privileged mode: read/write. */
    185 #define PTE_AP_USER_RW_KERNEL_RW        3
    186 
    187 
    188 /* pte_level0_t and pte_level1_t descriptor_type flags */
    189 
    190 /** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */
    191 #define PTE_DESCRIPTOR_NOT_PRESENT      0
    192 
    193 /** pte_level0_t coarse page table flag (used in descriptor_type). */
    194 #define PTE_DESCRIPTOR_COARSE_TABLE     1
    195 
    196 /** pte_level1_t small page table flag (used in descriptor type). */
    197 #define PTE_DESCRIPTOR_SMALL_PAGE       2
    198 
    199 
    200 /** Sets the address of level 0 page table.
    201  *
    202  * @param pt Pointer to the page table to set.
    203  *
    204  */
    205 NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
    206 {
    207         asm volatile (
    208                 "mcr p15, 0, %[pt], c2, c0, 0\n"
    209                 :: [pt] "r" (pt)
    210         );
    211 }
    212 
    213 
    214 /** Returns level 0 page table entry flags.
    215  *
    216  * @param pt Level 0 page table.
    217  * @param i  Index of the entry to return.
    218  *
    219  */
    220 NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i)
    221 {
    222         pte_level0_t *p = &pt[i].l0;
    223         int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT);
    224        
    225         return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) |
    226             (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) |
    227             (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT);
    228 }
    229 
    230 /** Returns level 1 page table entry flags.
    231  *
    232  * @param pt Level 1 page table.
    233  * @param i  Index of the entry to return.
    234  *
    235  */
    236 NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i)
    237 {
    238         pte_level1_t *p = &pt[i].l1;
    239        
    240         int dt = p->descriptor_type;
    241         int ap = p->access_permission_0;
    242        
    243         return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) |
    244             ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) |
    245             ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT) |
    246             ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT) |
    247             ((ap != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT) |
    248             ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT) |
    249             ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT) |
    250             (1 << PAGE_EXEC_SHIFT) |
    251             (p->bufferable << PAGE_CACHEABLE);
    252 }
    253 
    254 /** Sets flags of level 0 page table entry.
    255  *
    256  * @param pt    level 0 page table
    257  * @param i     index of the entry to be changed
    258  * @param flags new flags
    259  *
    260  */
    261 NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags)
    262 {
    263         pte_level0_t *p = &pt[i].l0;
    264        
    265         if (flags & PAGE_NOT_PRESENT) {
    266                 p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
    267                 /*
    268                  * Ensures that the entry will be recognized as valid when
    269                  * PTE_VALID_ARCH applied.
    270                  */
    271                 p->should_be_zero = 1;
    272         } else {
    273                 p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
    274                 p->should_be_zero = 0;
    275         }
    276 }
    277 
    278 NO_TRACE static inline void set_pt_level0_present(pte_t *pt, size_t i)
    279 {
    280         pte_level0_t *p = &pt[i].l0;
    281 
    282         p->should_be_zero = 0;
    283         write_barrier();
    284         p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
    285 }
    286 
    287 /** Sets flags of level 1 page table entry.
    288  *
    289  * We use same access rights for the whole page. When page
    290  * is not preset we store 1 in acess_rigts_3 so that at least
    291  * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH).
    292  *
    293  * @param pt    Level 1 page table.
    294  * @param i     Index of the entry to be changed.
    295  * @param flags New flags.
    296  *
    297  */
    298 NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags)
    299 {
    300         pte_level1_t *p = &pt[i].l1;
    301        
    302         if (flags & PAGE_NOT_PRESENT)
    303                 p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
    304         else
    305                 p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
    306        
    307         p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
    308        
    309         /* default access permission */
    310         p->access_permission_0 = p->access_permission_1 =
    311             p->access_permission_2 = p->access_permission_3 =
    312             PTE_AP_USER_NO_KERNEL_RW;
    313        
    314         if (flags & PAGE_USER)  {
    315                 if (flags & PAGE_READ) {
    316                         p->access_permission_0 = p->access_permission_1 =
    317                             p->access_permission_2 = p->access_permission_3 =
    318                             PTE_AP_USER_RO_KERNEL_RW;
    319                 }
    320                 if (flags & PAGE_WRITE) {
    321                         p->access_permission_0 = p->access_permission_1 =
    322                             p->access_permission_2 = p->access_permission_3 =
    323                             PTE_AP_USER_RW_KERNEL_RW;
    324                 }
    325         }
    326 }
    327 
    328 NO_TRACE static inline void set_pt_level1_present(pte_t *pt, size_t i)
    329 {
    330         pte_level1_t *p = &pt[i].l1;
    331 
    332         p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
    333 }
    334        
    335 extern void page_arch_init(void);
    336 
    337 #endif /* __ASM__ */
     131#if defined(PROCESSOR_armv7_a)
     132#include "page_armv7.h"
     133#elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
     134#include "page_armv4.h"
     135#endif
    338136
    339137#endif

  • kernel/arch/arm32/include/regutils.h

    r0d57c3e r96e01fbc  
    4141#define STATUS_REG_MODE_MASK         0x1f
    4242
     43#define CP15_R1_MMU_ENABLE_BIT       (1 << 0)
     44#define CP15_R1_ALIGNMENT_ENABLE_BIT (1 << 1)
     45#define CP15_R1_CACHE_ENABLE_BIT     (1 << 2)
     46#define CP15_R1_BRANCH_PREDICT_BIT   (1 << 11)
     47#define CP15_R1_INST_CACHE_BIT       (1 << 12)
    4348#define CP15_R1_HIGH_VECTORS_BIT     (1 << 13)
     49#define CP15_R1_ROUND_ROBIN_BIT      (1 << 14)
     50#define CP15_R1_HA_ENABLE_BIT        (1 << 17)
     51#define CP15_R1_WXN_BIT              (1 << 19) /* Only if virt. supported */
     52#define CP15_R1_UWXN_BIT             (1 << 20) /* Only if virt. supported */
     53#define CP15_R1_FI_BIT               (1 << 21)
     54#define CP15_R1_VE_BIT               (1 << 24)
     55#define CP15_R1_EE_BIT               (1 << 25)
     56#define CP15_R1_NMFI_BIT             (1 << 27)
     57#define CP15_R1_TRE_BIT              (1 << 28)
     58#define CP15_R1_AFE_BIT              (1 << 29)
    4459
    4560/* ARM Processor Operation Modes */

  • kernel/arch/arm32/src/arm32.c

    r0d57c3e r96e01fbc  
    4949#include <str.h>
    5050#include <arch/ras.h>
     51#include <sysinfo/sysinfo.h>
    5152
    5253/** Performs arm32-specific initialization before main_bsp() is called. */
    … …  
    116117{
    117118        machine_input_init();
     119        const char *platform = machine_get_platform_name();
     120
     121        sysinfo_set_item_data("platform", NULL, (void *) platform,
     122            str_size(platform));
    118123}
    119124

  • kernel/arch/arm32/src/cpu/cpu.c

    r0d57c3e r96e01fbc  
    4444/** Implementators (vendor) names */
    4545static const char *imp_data[] = {
    46         "?",                                    /* IMP_DATA_START_OFFSET */
    47         "ARM Ltd",                              /* 0x41 */
    48         "",                                     /* 0x42 */
    49         "",                                     /* 0x43 */
    50         "Digital Equipment Corporation",        /* 0x44 */
    51         "", "", "", "", "", "", "", "", "", "", /* 0x45 - 0x4e */
    52         "", "", "", "", "", "", "", "", "", "", /* 0x4f - 0x58 */
    53         "", "", "", "", "", "", "", "", "", "", /* 0x59 - 0x62 */
    54         "", "", "", "", "", "",                 /* 0x63 - 0x68 */
    55         "Intel Corporation"                     /* 0x69 */
     46        "?",                                     /* IMP_DATA_START_OFFSET */
     47        "ARM Limited",                           /* 0x41 */
     48        "", "",                                  /* 0x42 - 0x43 */
     49        "Digital Equipment Corporation",         /* 0x44 */
     50        "", "", "", "", "", "", "", "",          /* 0x45 - 0x4c */
     51        "Motorola, Freescale Semicondutor Inc.", /* 0x4d */
     52        "", "", "",                              /* 0x4e - 0x50 */
     53        "Qualcomm Inc.",                         /* 0x51 */
     54        "", "", "", "",                          /* 0x52 - 0x55 */
     55        "Marvell Semiconductor",                 /* 0x56 */
     56        "", "", "", "", "", "", "", "", "", "",  /* 0x57 - 0x60 */
     57        "", "", "", "", "", "", "", "",          /* 0x61 - 0x68 */
     58        "Intel Corporation"                      /* 0x69 */
    5659};
    5760
    … …  
    97100void cpu_arch_init(void)
    98101{
     102#if defined(PROCESSOR_armv7_a)
     103        uint32_t control_reg = 0;
     104        asm volatile (
     105                "mrc p15, 0, %[control_reg], c1, c0"
     106                : [control_reg] "=r" (control_reg)
     107        );
     108       
     109        /* Turn off tex remap */
     110        control_reg &= ~CP15_R1_TRE_BIT;
     111        /* Turn off accessed flag */
     112        control_reg &= ~(CP15_R1_AFE_BIT | CP15_R1_HA_ENABLE_BIT);
     113        /* Enable caching */
     114        control_reg |= CP15_R1_CACHE_ENABLE_BIT;
     115       
     116        asm volatile (
     117                "mcr p15, 0, %[control_reg], c1, c0"
     118                :: [control_reg] "r" (control_reg)
     119        );
     120#endif
    99121}
    100122
    … …  
    112134        cpu_arch_t * cpu_arch = &m->arch;
    113135
    114         if ((cpu_arch->imp_num) > 0 &&
    115             (cpu_arch->imp_num < (imp_data_length + IMP_DATA_START_OFFSET))) {
     136        const unsigned imp_offset = cpu_arch->imp_num - IMP_DATA_START_OFFSET;
     137
     138        if (imp_offset < imp_data_length) {
    116139                vendor = imp_data[cpu_arch->imp_num - IMP_DATA_START_OFFSET];
    117140        }
    118141
    119         if ((cpu_arch->arch_num) > 0 &&
    120             (cpu_arch->arch_num < arch_data_length)) {
     142        // TODO CPUs with arch_num == 0xf use CPUID scheme for identification
     143        if (cpu_arch->arch_num < arch_data_length) {
    121144                architecture = arch_data[cpu_arch->arch_num];
    122145        }

  • kernel/arch/arm32/src/exception.c

    r0d57c3e r96e01fbc  
    120120static void high_vectors(void)
    121121{
    122         uint32_t control_reg;
    123        
     122        uint32_t control_reg = 0;
     123       
     124#if defined(PROCESSOR_armv7_a)
     125        asm volatile (
     126                "mrc p15, 0, %[control_reg], c1, c0"
     127                : [control_reg] "=r" (control_reg)
     128        );
     129#elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
    124130        asm volatile (
    125131                "mrc p15, 0, %[control_reg], c1, c1"
    126132                : [control_reg] "=r" (control_reg)
    127133        );
     134#endif
    128135       
    129136        /* switch on the high vectors bit */
    130137        control_reg |= CP15_R1_HIGH_VECTORS_BIT;
    131138       
     139#if defined(PROCESSOR_armv7_a)
     140        asm volatile (
     141                "mcr p15, 0, %[control_reg], c1, c0"
     142                :: [control_reg] "r" (control_reg)
     143        );
     144#elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
    132145        asm volatile (
    133146                "mcr p15, 0, %[control_reg], c1, c1"
    134147                :: [control_reg] "r" (control_reg)
    135148        );
     149#endif
    136150}
    137151#endif

  • kernel/arch/arm32/src/machine_func.c

    r0d57c3e r96e01fbc  
    4242#include <arch/mach/integratorcp/integratorcp.h>
    4343#include <arch/mach/testarm/testarm.h>
     44#include <arch/mach/beagleboardxm/beagleboardxm.h>
    4445
    4546/** Pointer to machine_ops structure being used. */
    … …  
    5556#elif defined(MACHINE_integratorcp)
    5657        machine_ops = &icp_machine_ops;
     58#elif defined(MACHINE_beagleboardxm)
     59        machine_ops = &bbxm_machine_ops;
    5760#else
    5861#error Machine type not defined.
    … …  
    131134}
    132135
     136const char * machine_get_platform_name(void)
     137{
     138        if (machine_ops->machine_get_platform_name)
     139                return machine_ops->machine_get_platform_name();
     140        return NULL;
     141}
    133142/** @}
    134143 */

  • kernel/arch/arm32/src/mm/page.c

    r0d57c3e r96e01fbc  
    5252void page_arch_init(void)
    5353{
    54         int flags = PAGE_CACHEABLE;
     54        int flags = PAGE_CACHEABLE | PAGE_EXEC;
    5555        page_mapping_operations = &pt_mapping_operations;
    5656
    5757        page_table_lock(AS_KERNEL, true);
    5858       
    59         uintptr_t cur;
    60 
    6159        /* Kernel identity mapping */
    62         for (cur = PHYSMEM_START_ADDR;
    63             cur < min(config.identity_size, config.physmem_end);
     60        //FIXME: We need to consider the possibility that
     61        //identity_base > identity_size and physmem_end.
     62        //This might lead to overflow if identity_size is too big.
     63        for (uintptr_t cur = PHYSMEM_START_ADDR;
     64            cur < min(KA2PA(config.identity_base) +
     65                config.identity_size, config.physmem_end);
    6466            cur += FRAME_SIZE)
    6567                page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags);

  • kernel/arch/arm32/src/mm/page_fault.c

    r0d57c3e r96e01fbc  
    142142                panic("page_fault - instruction does not access memory "
    143143                    "(instr_code: %#0" PRIx32 ", badvaddr:%p).",
    144                     instr_union.pc, (void *) badvaddr);
     144                    *(uint32_t*)instr_union.instr, (void *) badvaddr);
    145145                return PF_ACCESS_EXEC;
    146146        }
    … …  
    162162        panic("page_fault - instruction doesn't access memory "
    163163            "(instr_code: %#0" PRIx32 ", badvaddr:%p).",
    164             instr_union.pc, (void *) badvaddr);
     164            *(uint32_t*)instr_union.instr, (void *) badvaddr);
    165165
    166166        return PF_ACCESS_EXEC;

  • kernel/genarch/Makefile.inc

    r0d57c3e r96e01fbc  
    101101endif
    102102
     103ifeq ($(CONFIG_AMDM37X_UART),y)
     104        GENARCH_SOURCES += \
     105                genarch/src/drivers/amdm37x_uart/amdm37x_uart.c
     106endif
     107
    103108ifeq ($(CONFIG_VIA_CUDA),y)
    104109        GENARCH_SOURCES += \

  • tools/mkuimage.py

    r0d57c3e r96e01fbc  
    120120        header.start_addr = start_addr  # Address of entry point
    121121        header.data_crc = data_crc
    122         header.os = 5                   # Linux
     122        header.os = 2                   # NetBSD
    123123        header.arch = 2                 # ARM
    124124        header.img_type = 2             # Kernel

  • uspace/Makefile

    r0d57c3e r96e01fbc  
    188188endif
    189189
     190ifeq ($(UARCH),arm32)
     191        DIRS += \
     192                drv/infrastructure/rootamdm37x
     193endif
     194
    190195## System libraries
    191196#

  • uspace/drv/bus/usb/ehci/ehci.ma

    r0d57c3e r96e01fbc  
     120 usb/host=ehci
    1210 pci/class=0c&subclass=03&progif=20

  • uspace/drv/bus/usb/ohci/ohci.ma

    r0d57c3e r96e01fbc  
     120 usb/host=ohci
    1210 pci/class=0c&subclass=03&progif=10

  • uspace/drv/bus/usb/ohci/ohci_regs.h

    r0d57c3e r96e01fbc  
    245245#define RHPS_PRSC_FLAG (1 << 20) /* port reset status change WC */
    246246#define RHPS_CHANGE_WC_MASK (0x1f0000)
    247 } __attribute__((packed)) ohci_regs_t;
     247} ohci_regs_t;
    248248#endif
    249249/**

  • uspace/lib/c/arch/arm32/Makefile.common

    r0d57c3e r96e01fbc  
    2828#
    2929
    30 GCC_CFLAGS += -ffixed-r9 -mtp=soft -fno-omit-frame-pointer -march=armv4
     30GCC_CFLAGS += -ffixed-r9 -mtp=soft -fno-omit-frame-pointer -march=$(subst _,-,$(PROCESSOR))
    3131
    3232ENDIANESS = LE

  • uspace/lib/usbdev/include/usb/dev/request.h

    r0d57c3e r96e01fbc  
    9393        uint8_t request;
    9494        /** Main parameter to the request. */
    95         union {
     95        union __attribute__ ((packed)) {
    9696                uint16_t value;
    9797                /* FIXME: add #ifdefs according to host endianness */
    98                 struct {
     98                struct __attribute__ ((packed)) {
    9999                        uint8_t value_low;
    100100                        uint8_t value_high;
    … …  
    108108        uint16_t length;
    109109} __attribute__ ((packed)) usb_device_request_setup_packet_t;
     110
     111int assert[(sizeof(usb_device_request_setup_packet_t) == 8) ? 1: -1];
    110112
    111113int usb_control_request_set(usb_pipe_t *,
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