Changes in kernel/arch/sparc64/include/atomic.h [7a0359b:986c24c] in mainline

File:

• kernel/arch/sparc64/include/atomic.h (modified) (3 diffs)

kernel/arch/sparc64/include/atomic.h

@@ -27 +27 @@
  */
 
-/** @addtogroup sparc64
+/** @addtogroup sparc64 
  * @{
  */
@@ -37 +37 @@
 
 #include <arch/barrier.h>
-#include <typedefs.h>
+#include <arch/types.h>
 #include <preemption.h>
-#include <trace.h>
 
 /** Atomic add operation.
@@ -46 +45 @@
  *
  * @param val Atomic variable.
- * @param i   Signed value to be added.
+ * @param i Signed value to be added.
  *
  * @return Value of the atomic variable as it existed before addition.
- *
  */
-NO_TRACE static inline atomic_count_t atomic_add(atomic_t *val,
-    atomic_count_t i)
+static inline long atomic_add(atomic_t *val, int i)
 {
-        atomic_count_t a;
-        atomic_count_t b;
-        
+        uint64_t a, b;
+
         do {
-                volatile uintptr_t ptr = (uintptr_t) &val->count;
-                
-                a = *((atomic_count_t *) ptr);
+                volatile uintptr_t x = (uint64_t) &val->count;
+
+                a = *((uint64_t *) x);
                 b = a + i;
-                
-                asm volatile (
-                        "casx %0, %2, %1\n"
-                        : "+m" (*((atomic_count_t *) ptr)),
-                      "+r" (b)
-                    : "r" (a)
-                );
+                asm volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *)x)),
+                    "+r" (b) : "r" (a));
         } while (a != b);
-        
+
         return a;
 }
 
-NO_TRACE static inline atomic_count_t atomic_preinc(atomic_t *val)
+static inline long atomic_preinc(atomic_t *val)
 {
         return atomic_add(val, 1) + 1;
 }
 
-NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val)
+static inline long atomic_postinc(atomic_t *val)
 {
         return atomic_add(val, 1);
 }
 
-NO_TRACE static inline atomic_count_t atomic_predec(atomic_t *val)
+static inline long atomic_predec(atomic_t *val)
 {
         return atomic_add(val, -1) - 1;
 }
 
-NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val)
+static inline long atomic_postdec(atomic_t *val)
 {
         return atomic_add(val, -1);
 }
 
-NO_TRACE static inline void atomic_inc(atomic_t *val)
+static inline void atomic_inc(atomic_t *val)
 {
         (void) atomic_add(val, 1);
 }
 
-NO_TRACE static inline void atomic_dec(atomic_t *val)
+static inline void atomic_dec(atomic_t *val)
 {
         (void) atomic_add(val, -1);
 }
 
-NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val)
+static inline long test_and_set(atomic_t *val)
 {
-        atomic_count_t v = 1;
-        volatile uintptr_t ptr = (uintptr_t) &val->count;
-        
-        asm volatile (
-                "casx %0, %2, %1\n"
-                : "+m" (*((atomic_count_t *) ptr)),
-              "+r" (v)
-            : "r" (0)
-        );
-        
+        uint64_t v = 1;
+        volatile uintptr_t x = (uint64_t) &val->count;
+
+        asm volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *) x)),
+            "+r" (v) : "r" (0));
+
         return v;
 }
 
-NO_TRACE static inline void atomic_lock_arch(atomic_t *val)
+static inline void atomic_lock_arch(atomic_t *val)
 {
-        atomic_count_t tmp1 = 1;
-        atomic_count_t tmp2 = 0;
-        
-        volatile uintptr_t ptr = (uintptr_t) &val->count;
-        
+        uint64_t tmp1 = 1;
+        uint64_t tmp2 = 0;
+
+        volatile uintptr_t x = (uint64_t) &val->count;
+
         preemption_disable();
-        
+
         asm volatile (
-                "0:\n"
-                        "casx %0, %3, %1\n"
-                        "brz %1, 2f\n"
-                        "nop\n"
-                "1:\n"
-                        "ldx %0, %2\n"
-                        "brz %2, 0b\n"
-                        "nop\n"
-                        "ba,a %%xcc, 1b\n"
-                "2:\n"
-                : "+m" (*((atomic_count_t *) ptr)),
-                  "+r" (tmp1),
-                  "+r" (tmp2)
-                : "r" (0)
+        "0:\n"
+                "casx %0, %3, %1\n"
+                "brz %1, 2f\n"
+                "nop\n"
+        "1:\n"
+                "ldx %0, %2\n"
+                "brz %2, 0b\n"
+                "nop\n"
+                "ba %%xcc, 1b\n"
+                "nop\n"
+        "2:\n"
+                : "+m" (*((uint64_t *) x)), "+r" (tmp1), "+r" (tmp2) : "r" (0)
         );