Changeset 98c4c16 in mainline
- Timestamp:
- 2019-07-02T20:30:17Z (5 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 9675296
- Parents:
- 5a5269d
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
boot/arch/arm32/src/asm.S
r5a5269d r98c4c16 32 32 .section BOOTSTRAP 33 33 34 #define CP15_C1_U 22 35 #define CP15_C1_IC 12 36 #define CP15_C1_BP 11 37 #define CP15_C1_DC 2 38 34 39 SYMBOL(start) 40 41 #ifdef PROCESSOR_ARCH_armv6 42 /* 43 * Enable unaligned doubleword memory accesses (STRD/LDRD) if the 44 * processor supports it. Note that that boils down to ARMv6 processors 45 * only as the older architectures require doubleword alignment and 46 * ARMv7 always assumes the U bit is 1. 47 */ 48 mrc p15, 0, r0, c1, c0, 0 49 orr r0, r0, #(1 << CP15_C1_U) 50 mcr p15, 0, r0, c1, c0, 0 51 #endif 52 35 53 ldr sp, =boot_stack 36 54 b bootstrap … … 59 77 # r0 is kernel entry point 60 78 # r1 is pointer to the bootinfo structure 61 62 #define CP15_C1_IC 1263 #define CP15_C1_BP 1164 #define CP15_C1_DC 265 66 79 67 80 #ifndef PROCESSOR_ARCH_armv7_a
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