Changes in kernel/arch/ia32/include/smp/apic.h [d99c1d2:99718a2e] in mainline
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kernel/arch/ia32/include/smp/apic.h (modified) (10 diffs)
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kernel/arch/ia32/include/smp/apic.h
rd99c1d2 r99718a2e 27 27 */ 28 28 29 /** @addtogroup ia32 29 /** @addtogroup ia32 30 30 * @{ 31 31 */ … … 39 39 #include <cpu.h> 40 40 41 #define FIXED (0<<0)42 #define LOPRI (1<<0)43 44 #define APIC_ID_COUNT 41 #define FIXED (0 << 0) 42 #define LOPRI (1 << 0) 43 44 #define APIC_ID_COUNT 16 45 45 46 46 /* local APIC macros */ 47 #define IPI_INIT 48 #define IPI_STARTUP 47 #define IPI_INIT 0 48 #define IPI_STARTUP 0 49 49 50 50 /** Delivery modes. */ 51 #define DELMOD_FIXED 52 #define DELMOD_LOWPRI 53 #define DELMOD_SMI 51 #define DELMOD_FIXED 0x0 52 #define DELMOD_LOWPRI 0x1 53 #define DELMOD_SMI 0x2 54 54 /* 0x3 reserved */ 55 #define DELMOD_NMI 56 #define DELMOD_INIT 57 #define DELMOD_STARTUP 58 #define DELMOD_EXTINT 55 #define DELMOD_NMI 0x4 56 #define DELMOD_INIT 0x5 57 #define DELMOD_STARTUP 0x6 58 #define DELMOD_EXTINT 0x7 59 59 60 60 /** Destination modes. */ 61 #define DESTMOD_PHYS 62 #define DESTMOD_LOGIC 61 #define DESTMOD_PHYS 0x0 62 #define DESTMOD_LOGIC 0x1 63 63 64 64 /** Trigger Modes. */ 65 #define TRIGMOD_EDGE 66 #define TRIGMOD_LEVEL 65 #define TRIGMOD_EDGE 0x0 66 #define TRIGMOD_LEVEL 0x1 67 67 68 68 /** Levels. */ 69 #define LEVEL_DEASSERT 70 #define LEVEL_ASSERT 69 #define LEVEL_DEASSERT 0x0 70 #define LEVEL_ASSERT 0x1 71 71 72 72 /** Destination Shorthands. */ 73 #define SHORTHAND_NONE 74 #define SHORTHAND_SELF 75 #define SHORTHAND_ALL_INCL 76 #define SHORTHAND_ALL_EXCL 73 #define SHORTHAND_NONE 0x0 74 #define SHORTHAND_SELF 0x1 75 #define SHORTHAND_ALL_INCL 0x2 76 #define SHORTHAND_ALL_EXCL 0x3 77 77 78 78 /** Interrupt Input Pin Polarities. */ 79 #define POLARITY_HIGH 80 #define POLARITY_LOW 79 #define POLARITY_HIGH 0x0 80 #define POLARITY_LOW 0x1 81 81 82 82 /** Divide Values. (Bit 2 is always 0) */ 83 #define DIVIDE_2 84 #define DIVIDE_4 85 #define DIVIDE_8 86 #define DIVIDE_16 87 #define DIVIDE_32 88 #define DIVIDE_64 89 #define DIVIDE_128 90 #define DIVIDE_1 83 #define DIVIDE_2 0x0 84 #define DIVIDE_4 0x1 85 #define DIVIDE_8 0x2 86 #define DIVIDE_16 0x3 87 #define DIVIDE_32 0x8 88 #define DIVIDE_64 0x9 89 #define DIVIDE_128 0xa 90 #define DIVIDE_1 0xb 91 91 92 92 /** Timer Modes. */ 93 #define TIMER_ONESHOT 94 #define TIMER_PERIODIC 93 #define TIMER_ONESHOT 0x0 94 #define TIMER_PERIODIC 0x1 95 95 96 96 /** Delivery status. */ 97 #define DELIVS_IDLE 98 #define DELIVS_PENDING 97 #define DELIVS_IDLE 0x0 98 #define DELIVS_PENDING 0x1 99 99 100 100 /** Destination masks. */ 101 #define DEST_ALL 101 #define DEST_ALL 0xff 102 102 103 103 /** Dest format models. */ 104 #define MODEL_FLAT 105 #define MODEL_CLUSTER 104 #define MODEL_FLAT 0xf 105 #define MODEL_CLUSTER 0x0 106 106 107 107 /** Interrupt Command Register. */ 108 #define ICRlo (0x300 / sizeof(uint32_t)) 109 #define ICRhi (0x310 / sizeof(uint32_t)) 108 #define ICRlo (0x300 / sizeof(uint32_t)) 109 #define ICRhi (0x310 / sizeof(uint32_t)) 110 110 111 typedef struct { 111 112 union { 112 113 uint32_t lo; 113 114 struct { 114 uint8_t vector; 115 unsigned delmod : 3;/**< Delivery Mode. */116 unsigned destmod : 1;/**< Destination Mode. */117 unsigned delivs : 1;/**< Delivery status (RO). */118 unsigned : 1;/**< Reserved. */119 unsigned level : 1;/**< Level. */120 unsigned trigger_mode : 1;/**< Trigger Mode. */121 unsigned : 2;/**< Reserved. */122 unsigned shorthand : 2;/**< Destination Shorthand. */123 unsigned : 12;/**< Reserved. */115 uint8_t vector; /**< Interrupt Vector. */ 116 unsigned int delmod : 3; /**< Delivery Mode. */ 117 unsigned int destmod : 1; /**< Destination Mode. */ 118 unsigned int delivs : 1; /**< Delivery status (RO). */ 119 unsigned int : 1; /**< Reserved. */ 120 unsigned int level : 1; /**< Level. */ 121 unsigned int trigger_mode : 1; /**< Trigger Mode. */ 122 unsigned int : 2; /**< Reserved. */ 123 unsigned int shorthand : 2; /**< Destination Shorthand. */ 124 unsigned int : 12; /**< Reserved. */ 124 125 } __attribute__ ((packed)); 125 126 }; … … 127 128 uint32_t hi; 128 129 struct { 129 unsigned : 24;/**< Reserved. */130 uint8_t dest; 130 unsigned int : 24; /**< Reserved. */ 131 uint8_t dest; /**< Destination field. */ 131 132 } __attribute__ ((packed)); 132 133 }; … … 134 135 135 136 /* End Of Interrupt. */ 136 #define EOI 137 #define EOI (0x0b0 / sizeof(uint32_t)) 137 138 138 139 /** Error Status Register. */ 139 #define ESR (0x280 / sizeof(uint32_t)) 140 #define ESR (0x280 / sizeof(uint32_t)) 141 140 142 typedef union { 141 143 uint32_t value; 142 144 uint8_t err_bitmap; 143 145 struct { 144 unsigned send_checksum_error : 1;145 unsigned receive_checksum_error : 1;146 unsigned send_accept_error : 1;147 unsigned receive_accept_error : 1;148 unsigned : 1;149 unsigned send_illegal_vector : 1;150 unsigned received_illegal_vector : 1;151 unsigned i llegal_register_address : 1;152 unsigned : 24;146 unsigned int send_checksum_error : 1; 147 unsigned int receive_checksum_error : 1; 148 unsigned int send_accept_error : 1; 149 unsigned int receive_accept_error : 1; 150 unsigned int : 1; 151 unsigned int send_illegal_vector : 1; 152 unsigned int received_illegal_vector : 1; 153 unsigned int illegal_register_address : 1; 154 unsigned int : 24; 153 155 } __attribute__ ((packed)); 154 156 } esr_t; 155 157 156 158 /* Task Priority Register */ 157 #define TPR (0x080 / sizeof(uint32_t)) 158 typedef union { 159 uint32_t value; 160 struct { 161 unsigned pri_sc : 4; /**< Task Priority Sub-Class. */ 162 unsigned pri : 4; /**< Task Priority. */ 159 #define TPR (0x080 / sizeof(uint32_t)) 160 161 typedef union { 162 uint32_t value; 163 struct { 164 unsigned int pri_sc : 4; /**< Task Priority Sub-Class. */ 165 unsigned int pri : 4; /**< Task Priority. */ 163 166 } __attribute__ ((packed)); 164 167 } tpr_t; 165 168 166 169 /** Spurious-Interrupt Vector Register. */ 167 #define SVR (0x0f0 / sizeof(uint32_t)) 168 typedef union { 169 uint32_t value; 170 struct { 171 uint8_t vector; /**< Spurious Vector. */ 172 unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable. */ 173 unsigned focus_checking : 1; /**< Focus Processor Checking. */ 174 unsigned : 22; /**< Reserved. */ 170 #define SVR (0x0f0 / sizeof(uint32_t)) 171 172 typedef union { 173 uint32_t value; 174 struct { 175 uint8_t vector; /**< Spurious Vector. */ 176 unsigned int lapic_enabled : 1; /**< APIC Software Enable/Disable. */ 177 unsigned int focus_checking : 1; /**< Focus Processor Checking. */ 178 unsigned int : 22; /**< Reserved. */ 175 179 } __attribute__ ((packed)); 176 180 } svr_t; 177 181 178 182 /** Time Divide Configuration Register. */ 179 #define TDCR (0x3e0 / sizeof(uint32_t)) 180 typedef union { 181 uint32_t value; 182 struct { 183 unsigned div_value : 4; /**< Divide Value, bit 2 is always 0. */ 184 unsigned : 28; /**< Reserved. */ 183 #define TDCR (0x3e0 / sizeof(uint32_t)) 184 185 typedef union { 186 uint32_t value; 187 struct { 188 unsigned int div_value : 4; /**< Divide Value, bit 2 is always 0. */ 189 unsigned int : 28; /**< Reserved. */ 185 190 } __attribute__ ((packed)); 186 191 } tdcr_t; 187 192 188 193 /* Initial Count Register for Timer */ 189 #define ICRT 194 #define ICRT (0x380 / sizeof(uint32_t)) 190 195 191 196 /* Current Count Register for Timer */ 192 #define CCRT 197 #define CCRT (0x390 / sizeof(uint32_t)) 193 198 194 199 /** LVT Timer register. */ 195 #define LVT_Tm (0x320 / sizeof(uint32_t)) 196 typedef union { 197 uint32_t value; 198 struct { 199 uint8_t vector; /**< Local Timer Interrupt vector. */ 200 unsigned : 4; /**< Reserved. */ 201 unsigned delivs : 1; /**< Delivery status (RO). */ 202 unsigned : 3; /**< Reserved. */ 203 unsigned masked : 1; /**< Interrupt Mask. */ 204 unsigned mode : 1; /**< Timer Mode. */ 205 unsigned : 14; /**< Reserved. */ 200 #define LVT_Tm (0x320 / sizeof(uint32_t)) 201 202 typedef union { 203 uint32_t value; 204 struct { 205 uint8_t vector; /**< Local Timer Interrupt vector. */ 206 unsigned int : 4; /**< Reserved. */ 207 unsigned int delivs : 1; /**< Delivery status (RO). */ 208 unsigned int : 3; /**< Reserved. */ 209 unsigned int masked : 1; /**< Interrupt Mask. */ 210 unsigned int mode : 1; /**< Timer Mode. */ 211 unsigned int : 14; /**< Reserved. */ 206 212 } __attribute__ ((packed)); 207 213 } lvt_tm_t; 208 214 209 215 /** LVT LINT registers. */ 210 #define LVT_LINT0 (0x350 / sizeof(uint32_t)) 211 #define LVT_LINT1 (0x360 / sizeof(uint32_t)) 212 typedef union { 213 uint32_t value; 214 struct { 215 uint8_t vector; /**< LINT Interrupt vector. */ 216 unsigned delmod : 3; /**< Delivery Mode. */ 217 unsigned : 1; /**< Reserved. */ 218 unsigned delivs : 1; /**< Delivery status (RO). */ 219 unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ 220 unsigned irr : 1; /**< Remote IRR (RO). */ 221 unsigned trigger_mode : 1; /**< Trigger Mode. */ 222 unsigned masked : 1; /**< Interrupt Mask. */ 223 unsigned : 15; /**< Reserved. */ 216 #define LVT_LINT0 (0x350 / sizeof(uint32_t)) 217 #define LVT_LINT1 (0x360 / sizeof(uint32_t)) 218 219 typedef union { 220 uint32_t value; 221 struct { 222 uint8_t vector; /**< LINT Interrupt vector. */ 223 unsigned int delmod : 3; /**< Delivery Mode. */ 224 unsigned int : 1; /**< Reserved. */ 225 unsigned int delivs : 1; /**< Delivery status (RO). */ 226 unsigned int intpol : 1; /**< Interrupt Input Pin Polarity. */ 227 unsigned int irr : 1; /**< Remote IRR (RO). */ 228 unsigned int trigger_mode : 1; /**< Trigger Mode. */ 229 unsigned int masked : 1; /**< Interrupt Mask. */ 230 unsigned int : 15; /**< Reserved. */ 224 231 } __attribute__ ((packed)); 225 232 } lvt_lint_t; 226 233 227 234 /** LVT Error register. */ 228 #define LVT_Err (0x370 / sizeof(uint32_t)) 229 typedef union { 230 uint32_t value; 231 struct { 232 uint8_t vector; /**< Local Timer Interrupt vector. */ 233 unsigned : 4; /**< Reserved. */ 234 unsigned delivs : 1; /**< Delivery status (RO). */ 235 unsigned : 3; /**< Reserved. */ 236 unsigned masked : 1; /**< Interrupt Mask. */ 237 unsigned : 15; /**< Reserved. */ 235 #define LVT_Err (0x370 / sizeof(uint32_t)) 236 237 typedef union { 238 uint32_t value; 239 struct { 240 uint8_t vector; /**< Local Timer Interrupt vector. */ 241 unsigned int : 4; /**< Reserved. */ 242 unsigned int delivs : 1; /**< Delivery status (RO). */ 243 unsigned int : 3; /**< Reserved. */ 244 unsigned int masked : 1; /**< Interrupt Mask. */ 245 unsigned int : 15; /**< Reserved. */ 238 246 } __attribute__ ((packed)); 239 247 } lvt_error_t; 240 248 241 249 /** Local APIC ID Register. */ 242 #define L_APIC_ID (0x020 / sizeof(uint32_t)) 243 typedef union { 244 uint32_t value; 245 struct { 246 unsigned : 24; /**< Reserved. */ 247 uint8_t apic_id; /**< Local APIC ID. */ 250 #define L_APIC_ID (0x020 / sizeof(uint32_t)) 251 252 typedef union { 253 uint32_t value; 254 struct { 255 unsigned int : 24; /**< Reserved. */ 256 uint8_t apic_id; /**< Local APIC ID. */ 248 257 } __attribute__ ((packed)); 249 258 } l_apic_id_t; 250 259 251 260 /** Local APIC Version Register */ 252 #define LAVR (0x030 / sizeof(uint32_t)) 253 #define LAVR_Mask 0xff 254 #define is_local_apic(x) (((x) & LAVR_Mask & 0xf0) == 0x1) 255 #define is_82489DX_apic(x) ((((x) & LAVR_Mask & 0xf0) == 0x0)) 256 #define is_local_xapic(x) (((x) & LAVR_Mask) == 0x14) 261 #define LAVR (0x030 / sizeof(uint32_t)) 262 #define LAVR_Mask 0xff 263 264 #define is_local_apic(x) (((x) & LAVR_Mask & 0xf0) == 0x1) 265 #define is_82489DX_apic(x) ((((x) & LAVR_Mask & 0xf0) == 0x0)) 266 #define is_local_xapic(x) (((x) & LAVR_Mask) == 0x14) 257 267 258 268 /** Logical Destination Register. */ 259 #define LDR (0x0d0 / sizeof(uint32_t)) 260 typedef union { 261 uint32_t value; 262 struct { 263 unsigned : 24; /**< Reserved. */ 264 uint8_t id; /**< Logical APIC ID. */ 269 #define LDR (0x0d0 / sizeof(uint32_t)) 270 271 typedef union { 272 uint32_t value; 273 struct { 274 unsigned int : 24; /**< Reserved. */ 275 uint8_t id; /**< Logical APIC ID. */ 265 276 } __attribute__ ((packed)); 266 277 } ldr_t; 267 278 268 279 /** Destination Format Register. */ 269 #define DFR (0x0e0 / sizeof(uint32_t)) 270 typedef union { 271 uint32_t value; 272 struct { 273 unsigned : 28; /**< Reserved, all ones. */ 274 unsigned model : 4; /**< Model. */ 280 #define DFR (0x0e0 / sizeof(uint32_t)) 281 282 typedef union { 283 uint32_t value; 284 struct { 285 unsigned int : 28; /**< Reserved, all ones. */ 286 unsigned int model : 4; /**< Model. */ 275 287 } __attribute__ ((packed)); 276 288 } dfr_t; 277 289 278 290 /* IO APIC */ 279 #define IOREGSEL 280 #define IOWIN 281 282 #define IOAPICID 283 #define IOAPICVER 284 #define IOAPICARB 285 #define IOREDTBL 291 #define IOREGSEL (0x00 / sizeof(uint32_t)) 292 #define IOWIN (0x10 / sizeof(uint32_t)) 293 294 #define IOAPICID 0x00 295 #define IOAPICVER 0x01 296 #define IOAPICARB 0x02 297 #define IOREDTBL 0x10 286 298 287 299 /** I/O Register Select Register. */ … … 289 301 uint32_t value; 290 302 struct { 291 uint8_t reg_addr; 292 unsigned : 24;/**< Reserved. */303 uint8_t reg_addr; /**< APIC Register Address. */ 304 unsigned int : 24; /**< Reserved. */ 293 305 } __attribute__ ((packed)); 294 306 } io_regsel_t; … … 299 311 uint32_t lo; 300 312 struct { 301 uint8_t intvec; 302 unsigned delmod : 3;/**< Delivery Mode. */303 unsigned destmod : 1;/**< Destination mode. */304 unsigned delivs : 1;/**< Delivery status (RO). */305 unsigned int pol : 1;/**< Interrupt Input Pin Polarity. */306 unsigned i rr : 1;/**< Remote IRR (RO). */307 unsigned trigger_mode : 1;/**< Trigger Mode. */308 unsigned masked : 1;/**< Interrupt Mask. */309 unsigned : 15;/**< Reserved. */313 uint8_t intvec; /**< Interrupt Vector. */ 314 unsigned int delmod : 3; /**< Delivery Mode. */ 315 unsigned int destmod : 1; /**< Destination mode. */ 316 unsigned int delivs : 1; /**< Delivery status (RO). */ 317 unsigned int intpol : 1; /**< Interrupt Input Pin Polarity. */ 318 unsigned int irr : 1; /**< Remote IRR (RO). */ 319 unsigned int trigger_mode : 1; /**< Trigger Mode. */ 320 unsigned int masked : 1; /**< Interrupt Mask. */ 321 unsigned int : 15; /**< Reserved. */ 310 322 } __attribute__ ((packed)); 311 323 }; … … 313 325 uint32_t hi; 314 326 struct { 315 unsigned : 24;/**< Reserved. */316 uint8_t dest : 8; 327 unsigned int : 24; /**< Reserved. */ 328 uint8_t dest : 8; /**< Destination Field. */ 317 329 } __attribute__ ((packed)); 318 330 }; … … 325 337 uint32_t value; 326 338 struct { 327 unsigned : 24;/**< Reserved. */328 unsigned apic_id : 4;/**< IO APIC ID. */329 unsigned : 4;/**< Reserved. */339 unsigned int : 24; /**< Reserved. */ 340 unsigned int apic_id : 4; /**< IO APIC ID. */ 341 unsigned int : 4; /**< Reserved. */ 330 342 } __attribute__ ((packed)); 331 343 } io_apic_id_t; … … 335 347 336 348 extern uint32_t apic_id_mask; 349 extern uint8_t bsp_l_apic; 337 350 338 351 extern void apic_init(void); … … 340 353 extern void l_apic_init(void); 341 354 extern void l_apic_eoi(void); 342 extern int l_apic_broadcast_custom_ipi(uint8_t vector);343 extern int l_apic_send_init_ipi(uint8_t apicid);355 extern int l_apic_broadcast_custom_ipi(uint8_t); 356 extern int l_apic_send_init_ipi(uint8_t); 344 357 extern void l_apic_debug(void); 345 extern uint8_t l_apic_id(void); 346 347 extern uint32_t io_apic_read(uint8_t address); 348 extern void io_apic_write(uint8_t address , uint32_t x); 349 extern void io_apic_change_ioredtbl(uint8_t pin, uint8_t dest, uint8_t v, int flags); 350 extern void io_apic_disable_irqs(uint16_t irqmask); 351 extern void io_apic_enable_irqs(uint16_t irqmask); 358 359 extern uint32_t io_apic_read(uint8_t); 360 extern void io_apic_write(uint8_t, uint32_t); 361 extern void io_apic_change_ioredtbl(uint8_t pin, uint8_t dest, uint8_t v, unsigned int); 362 extern void io_apic_disable_irqs(uint16_t); 363 extern void io_apic_enable_irqs(uint16_t); 352 364 353 365 #endif
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