Changes in kernel/arch/ia32/src/smp/smp.c [e3ce39b:99718a2e] in mainline
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kernel/arch/ia32/src/smp/smp.c
re3ce39b r99718a2e 62 62 void smp_init(void) 63 63 { 64 uintptr_t l_apic_address, io_apic_address;65 66 64 if (acpi_madt) { 67 65 acpi_madt_parse(); 68 66 ops = &madt_config_operations; 69 67 } 68 70 69 if (config.cpu_count == 1) { 71 70 mps_init(); 72 71 ops = &mps_config_operations; 73 72 } 74 75 l_apic_address = (uintptr_t) frame_alloc(ONE_FRAME, 76 FRAME_ATOMIC | FRAME_KA); 77 if (!l_apic_address) 78 panic("Cannot allocate address for l_apic."); 79 80 io_apic_address = (uintptr_t) frame_alloc(ONE_FRAME, 81 FRAME_ATOMIC | FRAME_KA); 82 if (!io_apic_address) 83 panic("Cannot allocate address for io_apic."); 84 73 85 74 if (config.cpu_count > 1) { 86 page_table_lock(AS_KERNEL, true); 87 page_mapping_insert(AS_KERNEL, l_apic_address, 88 (uintptr_t) l_apic, PAGE_NOT_CACHEABLE | PAGE_WRITE); 89 page_mapping_insert(AS_KERNEL, io_apic_address, 90 (uintptr_t) io_apic, PAGE_NOT_CACHEABLE | PAGE_WRITE); 91 page_table_unlock(AS_KERNEL, true); 92 93 l_apic = (uint32_t *) l_apic_address; 94 io_apic = (uint32_t *) io_apic_address; 75 l_apic = (uint32_t *) hw_map((uintptr_t) l_apic, PAGE_SIZE); 76 io_apic = (uint32_t *) hw_map((uintptr_t) io_apic, PAGE_SIZE); 95 77 } 96 78 } … … 108 90 109 91 ASSERT(ops != NULL); 110 92 111 93 /* 112 94 * We need to access data in frame 0. 113 95 * We boldly make use of kernel address space mapping. 114 96 */ 115 97 116 98 /* 117 99 * Set the warm-reset vector to the real-mode address of 4K-aligned ap_boot() 118 100 */ 119 101 *((uint16_t *) (PA2KA(0x467 + 0))) = 120 (uint16_t) (((uintptr_t) ap_boot) >> 4); 121 *((uint16_t *) (PA2KA(0x467 + 2))) = 0; 102 (uint16_t) (((uintptr_t) ap_boot) >> 4); /* segment */ 103 *((uint16_t *) (PA2KA(0x467 + 2))) = 0; /* offset */ 122 104 123 105 /* … … 125 107 * BIOS will not do the POST after the INIT signal. 126 108 */ 127 pio_write_8((ioport8_t *) 0x70, 0xf);128 pio_write_8((ioport8_t *) 0x71, 0xa);129 109 pio_write_8((ioport8_t *) 0x70, 0xf); 110 pio_write_8((ioport8_t *) 0x71, 0xa); 111 130 112 pic_disable_irqs(0xffff); 131 113 apic_init(); 132 114 133 uint8_t apic = l_apic_id(); 134 135 for (i = 0; i < ops->cpu_count(); i++) { 136 descriptor_t *gdt_new; 137 115 for (i = 0; i < config.cpu_count; i++) { 138 116 /* 139 117 * Skip processors marked unusable. … … 141 119 if (!ops->cpu_enabled(i)) 142 120 continue; 143 121 144 122 /* 145 123 * The bootstrap processor is already up. … … 147 125 if (ops->cpu_bootstrap(i)) 148 126 continue; 149 150 if (ops->cpu_apic_id(i) == apic) {151 printf(" %s: bad processor entry #%u, will not send IPI "152 "to myself\n", __FUNCTION__,i);127 128 if (ops->cpu_apic_id(i) == bsp_l_apic) { 129 printf("kmp: bad processor entry #%u, will not send IPI " 130 "to myself\n", i); 153 131 continue; 154 132 } … … 162 140 * the memory subsystem 163 141 */ 164 gdt_new = (descriptor_t *) malloc(GDT_ITEMS * 165 sizeof(descriptor_t), FRAME_ATOMIC); 142 descriptor_t *gdt_new = 143 (descriptor_t *) malloc(GDT_ITEMS * sizeof(descriptor_t), 144 FRAME_ATOMIC); 166 145 if (!gdt_new) 167 146 panic("Cannot allocate memory for GDT."); 168 147 169 148 memcpy(gdt_new, gdt, GDT_ITEMS * sizeof(descriptor_t)); 170 149 memsetb(&gdt_new[TSS_DES], sizeof(descriptor_t), 0); … … 172 151 protected_ap_gdtr.base = KA2PA((uintptr_t) gdt_new); 173 152 gdtr.base = (uintptr_t) gdt_new; 174 153 175 154 if (l_apic_send_init_ipi(ops->cpu_apic_id(i))) { 176 155 /* … … 181 160 if (waitq_sleep_timeout(&ap_completion_wq, 1000000, 182 161 SYNCH_FLAGS_NONE) == ESYNCH_TIMEOUT) { 183 unsigned int cpu = (config.cpu_active > i) ?184 config.cpu_active : i;185 162 printf("%s: waiting for cpu%u (APIC ID = %d) " 186 "timed out\n", __FUNCTION__, cpu,163 "timed out\n", __FUNCTION__, i, 187 164 ops->cpu_apic_id(i)); 188 165 }
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