Changes in kernel/arch/amd64/include/asm.h [96b02eb9:99d6fd0] in mainline
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kernel/arch/amd64/include/asm.h (modified) (27 diffs)
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kernel/arch/amd64/include/asm.h
r96b02eb9 r99d6fd0 37 37 38 38 #include <config.h> 39 #include <arch/types.h> 39 40 #include <typedefs.h> 40 #include <arch/cpu.h> 41 #include <trace.h> 41 42 extern void asm_delay_loop(uint32_t t); 43 extern void asm_fake_loop(uint32_t t); 42 44 43 45 /** Return base address of current stack. … … 48 50 * 49 51 */ 50 NO_TRACEstatic inline uintptr_t get_stack_base(void)52 static inline uintptr_t get_stack_base(void) 51 53 { 52 54 uintptr_t v; … … 55 57 "andq %%rsp, %[v]\n" 56 58 : [v] "=r" (v) 57 : "0" (~((uint64_t) STACK_SIZE -1))59 : "0" (~((uint64_t) STACK_SIZE-1)) 58 60 ); 59 61 … … 61 63 } 62 64 63 NO_TRACE static inline void cpu_sleep(void) 64 { 65 asm volatile ( 66 "hlt\n" 67 ); 68 } 69 70 NO_TRACE static inline void __attribute__((noreturn)) cpu_halt(void) 71 { 72 while (true) { 73 asm volatile ( 74 "hlt\n" 75 ); 76 } 77 } 65 static inline void cpu_sleep(void) 66 { 67 asm volatile ("hlt\n"); 68 } 69 70 static inline void cpu_halt(void) 71 { 72 asm volatile ( 73 "0:\n" 74 " hlt\n" 75 " jmp 0b\n" 76 ); 77 } 78 78 79 79 80 /** Byte from port … … 85 86 * 86 87 */ 87 NO_TRACEstatic inline uint8_t pio_read_8(ioport8_t *port)88 static inline uint8_t pio_read_8(ioport8_t *port) 88 89 { 89 90 uint8_t val; … … 106 107 * 107 108 */ 108 NO_TRACEstatic inline uint16_t pio_read_16(ioport16_t *port)109 static inline uint16_t pio_read_16(ioport16_t *port) 109 110 { 110 111 uint16_t val; … … 127 128 * 128 129 */ 129 NO_TRACEstatic inline uint32_t pio_read_32(ioport32_t *port)130 static inline uint32_t pio_read_32(ioport32_t *port) 130 131 { 131 132 uint32_t val; … … 148 149 * 149 150 */ 150 NO_TRACEstatic inline void pio_write_8(ioport8_t *port, uint8_t val)151 static inline void pio_write_8(ioport8_t *port, uint8_t val) 151 152 { 152 153 asm volatile ( 153 154 "outb %b[val], %w[port]\n" 154 :: [val] "a" (val), 155 [port] "d" (port) 155 :: [val] "a" (val), [port] "d" (port) 156 156 ); 157 157 } … … 165 165 * 166 166 */ 167 NO_TRACEstatic inline void pio_write_16(ioport16_t *port, uint16_t val)167 static inline void pio_write_16(ioport16_t *port, uint16_t val) 168 168 { 169 169 asm volatile ( 170 170 "outw %w[val], %w[port]\n" 171 :: [val] "a" (val), 172 [port] "d" (port) 171 :: [val] "a" (val), [port] "d" (port) 173 172 ); 174 173 } … … 182 181 * 183 182 */ 184 NO_TRACEstatic inline void pio_write_32(ioport32_t *port, uint32_t val)183 static inline void pio_write_32(ioport32_t *port, uint32_t val) 185 184 { 186 185 asm volatile ( 187 186 "outl %[val], %w[port]\n" 188 :: [val] "a" (val), 189 [port] "d" (port) 187 :: [val] "a" (val), [port] "d" (port) 190 188 ); 191 189 } 192 190 193 191 /** Swap Hidden part of GS register with visible one */ 194 NO_TRACE static inline void swapgs(void) 195 { 196 asm volatile ( 197 "swapgs" 198 ); 192 static inline void swapgs(void) 193 { 194 asm volatile("swapgs"); 199 195 } 200 196 … … 207 203 * 208 204 */ 209 NO_TRACEstatic inline ipl_t interrupts_enable(void) {205 static inline ipl_t interrupts_enable(void) { 210 206 ipl_t v; 211 207 … … 228 224 * 229 225 */ 230 NO_TRACEstatic inline ipl_t interrupts_disable(void) {226 static inline ipl_t interrupts_disable(void) { 231 227 ipl_t v; 232 228 … … 248 244 * 249 245 */ 250 NO_TRACEstatic inline void interrupts_restore(ipl_t ipl) {246 static inline void interrupts_restore(ipl_t ipl) { 251 247 asm volatile ( 252 248 "pushq %[ipl]\n" … … 263 259 * 264 260 */ 265 NO_TRACEstatic inline ipl_t interrupts_read(void) {261 static inline ipl_t interrupts_read(void) { 266 262 ipl_t v; 267 263 … … 275 271 } 276 272 277 /** Check interrupts state.278 *279 * @return True if interrupts are disabled.280 *281 */282 NO_TRACE static inline bool interrupts_disabled(void)283 {284 ipl_t v;285 286 asm volatile (287 "pushfq\n"288 "popq %[v]\n"289 : [v] "=r" (v)290 );291 292 return ((v & RFLAGS_IF) == 0);293 }294 295 273 /** Write to MSR */ 296 NO_TRACEstatic inline void write_msr(uint32_t msr, uint64_t value)274 static inline void write_msr(uint32_t msr, uint64_t value) 297 275 { 298 276 asm volatile ( … … 304 282 } 305 283 306 NO_TRACE static inline sysarg_t read_msr(uint32_t msr)284 static inline unative_t read_msr(uint32_t msr) 307 285 { 308 286 uint32_t ax, dx; … … 317 295 } 318 296 297 319 298 /** Enable local APIC 320 299 * … … 322 301 * 323 302 */ 324 NO_TRACEstatic inline void enable_l_apic_in_msr()303 static inline void enable_l_apic_in_msr() 325 304 { 326 305 asm volatile ( … … 330 309 "orl $(0xfee00000),%%eax\n" 331 310 "wrmsr\n" 332 ::: "%eax", "%ecx", "%edx" 333 ); 311 ::: "%eax","%ecx","%edx" 312 ); 313 } 314 315 static inline uintptr_t * get_ip() 316 { 317 uintptr_t *ip; 318 319 asm volatile ( 320 "mov %%rip, %[ip]" 321 : [ip] "=r" (ip) 322 ); 323 324 return ip; 334 325 } 335 326 … … 339 330 * 340 331 */ 341 NO_TRACEstatic inline void invlpg(uintptr_t addr)332 static inline void invlpg(uintptr_t addr) 342 333 { 343 334 asm volatile ( 344 335 "invlpg %[addr]\n" 345 :: [addr] "m" (*(( sysarg_t *) addr))336 :: [addr] "m" (*((unative_t *) addr)) 346 337 ); 347 338 } … … 352 343 * 353 344 */ 354 NO_TRACEstatic inline void gdtr_load(ptr_16_64_t *gdtr_reg)345 static inline void gdtr_load(ptr_16_64_t *gdtr_reg) 355 346 { 356 347 asm volatile ( … … 365 356 * 366 357 */ 367 NO_TRACEstatic inline void gdtr_store(ptr_16_64_t *gdtr_reg)358 static inline void gdtr_store(ptr_16_64_t *gdtr_reg) 368 359 { 369 360 asm volatile ( … … 378 369 * 379 370 */ 380 NO_TRACEstatic inline void idtr_load(ptr_16_64_t *idtr_reg)371 static inline void idtr_load(ptr_16_64_t *idtr_reg) 381 372 { 382 373 asm volatile ( … … 390 381 * 391 382 */ 392 NO_TRACEstatic inline void tr_load(uint16_t sel)383 static inline void tr_load(uint16_t sel) 393 384 { 394 385 asm volatile ( … … 398 389 } 399 390 400 #define GEN_READ_REG(reg) NO_TRACE static inline sysarg_t read_ ##reg (void) \391 #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ 401 392 { \ 402 sysarg_t res; \393 unative_t res; \ 403 394 asm volatile ( \ 404 395 "movq %%" #reg ", %[res]" \ … … 408 399 } 409 400 410 #define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (sysarg_t regn) \401 #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ 411 402 { \ 412 403 asm volatile ( \ … … 435 426 GEN_WRITE_REG(dr7) 436 427 437 extern void asm_delay_loop(uint32_t); 438 extern void asm_fake_loop(uint32_t); 439 440 extern uintptr_t int_0; 441 extern uintptr_t int_1; 442 extern uintptr_t int_2; 443 extern uintptr_t int_3; 444 extern uintptr_t int_4; 445 extern uintptr_t int_5; 446 extern uintptr_t int_6; 447 extern uintptr_t int_7; 448 extern uintptr_t int_8; 449 extern uintptr_t int_9; 450 extern uintptr_t int_10; 451 extern uintptr_t int_11; 452 extern uintptr_t int_12; 453 extern uintptr_t int_13; 454 extern uintptr_t int_14; 455 extern uintptr_t int_15; 456 extern uintptr_t int_16; 457 extern uintptr_t int_17; 458 extern uintptr_t int_18; 459 extern uintptr_t int_19; 460 extern uintptr_t int_20; 461 extern uintptr_t int_21; 462 extern uintptr_t int_22; 463 extern uintptr_t int_23; 464 extern uintptr_t int_24; 465 extern uintptr_t int_25; 466 extern uintptr_t int_26; 467 extern uintptr_t int_27; 468 extern uintptr_t int_28; 469 extern uintptr_t int_29; 470 extern uintptr_t int_30; 471 extern uintptr_t int_31; 472 extern uintptr_t int_32; 473 extern uintptr_t int_33; 474 extern uintptr_t int_34; 475 extern uintptr_t int_35; 476 extern uintptr_t int_36; 477 extern uintptr_t int_37; 478 extern uintptr_t int_38; 479 extern uintptr_t int_39; 480 extern uintptr_t int_40; 481 extern uintptr_t int_41; 482 extern uintptr_t int_42; 483 extern uintptr_t int_43; 484 extern uintptr_t int_44; 485 extern uintptr_t int_45; 486 extern uintptr_t int_46; 487 extern uintptr_t int_47; 488 extern uintptr_t int_48; 489 extern uintptr_t int_49; 490 extern uintptr_t int_50; 491 extern uintptr_t int_51; 492 extern uintptr_t int_52; 493 extern uintptr_t int_53; 494 extern uintptr_t int_54; 495 extern uintptr_t int_55; 496 extern uintptr_t int_56; 497 extern uintptr_t int_57; 498 extern uintptr_t int_58; 499 extern uintptr_t int_59; 500 extern uintptr_t int_60; 501 extern uintptr_t int_61; 502 extern uintptr_t int_62; 503 extern uintptr_t int_63; 428 extern size_t interrupt_handler_size; 429 extern void interrupt_handlers(void); 504 430 505 431 #endif
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