Changeset 99e8fb7b in mainline
- Timestamp:
- 2013-12-31T19:08:48Z (11 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 7f620e8
- Parents:
- a44424f
- Location:
- uspace
- Files:
-
- 2 deleted
- 9 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/block/ahci/ahci.c
ra44424f r99e8fb7b 37 37 #include <ddf/log.h> 38 38 #include <device/hw_res_parsed.h> 39 #include < device/pci.h>39 #include <pci_dev_iface.h> 40 40 #include <sysinfo.h> 41 41 #include <ipc/irc.h> -
uspace/drv/bus/pci/pciintel/pci.c
ra44424f r99e8fb7b 153 153 154 154 155 static int pci_config_space_write_32(ddf_fun_t *fun, uint32_t address,155 static int config_space_write_32(ddf_fun_t *fun, uint32_t address, 156 156 uint32_t data) 157 157 { … … 162 162 } 163 163 164 static int pci_config_space_write_16(164 static int config_space_write_16( 165 165 ddf_fun_t *fun, uint32_t address, uint16_t data) 166 166 { … … 171 171 } 172 172 173 static int pci_config_space_write_8(173 static int config_space_write_8( 174 174 ddf_fun_t *fun, uint32_t address, uint8_t data) 175 175 { … … 180 180 } 181 181 182 static int pci_config_space_read_32(182 static int config_space_read_32( 183 183 ddf_fun_t *fun, uint32_t address, uint32_t *data) 184 184 { … … 189 189 } 190 190 191 static int pci_config_space_read_16(191 static int config_space_read_16( 192 192 ddf_fun_t *fun, uint32_t address, uint16_t *data) 193 193 { … … 198 198 } 199 199 200 static int pci_config_space_read_8(200 static int config_space_read_8( 201 201 ddf_fun_t *fun, uint32_t address, uint8_t *data) 202 202 { … … 217 217 218 218 static pci_dev_iface_t pci_dev_ops = { 219 .config_space_read_8 = & pci_config_space_read_8,220 .config_space_read_16 = & pci_config_space_read_16,221 .config_space_read_32 = & pci_config_space_read_32,222 .config_space_write_8 = & pci_config_space_write_8,223 .config_space_write_16 = & pci_config_space_write_16,224 .config_space_write_32 = & pci_config_space_write_32219 .config_space_read_8 = &config_space_read_8, 220 .config_space_read_16 = &config_space_read_16, 221 .config_space_read_32 = &config_space_read_32, 222 .config_space_write_8 = &config_space_write_8, 223 .config_space_write_16 = &config_space_write_16, 224 .config_space_write_32 = &config_space_write_32 225 225 }; 226 226 -
uspace/drv/bus/usb/ehci/res.c
ra44424f r99e8fb7b 43 43 #include <usb/debug.h> 44 44 #include <device/hw_res_parsed.h> 45 #include < device/pci.h>45 #include <pci_dev_iface.h> 46 46 47 47 #include "res.h" -
uspace/drv/bus/usb/uhci/res.c
ra44424f r99e8fb7b 39 39 #include <devman.h> 40 40 #include <device/hw_res_parsed.h> 41 #include < device/pci.h>41 #include <pci_dev_iface.h> 42 42 43 43 #include "res.h" -
uspace/drv/nic/e1k/e1k.c
ra44424f r99e8fb7b 50 50 #include <ddf/interrupt.h> 51 51 #include <device/hw_res_parsed.h> 52 #include < device/pci.h>52 #include <pci_dev_iface.h> 53 53 #include <nic.h> 54 54 #include <ops/nic.h> -
uspace/drv/nic/rtl8139/driver.c
ra44424f r99e8fb7b 41 41 #include <io/log.h> 42 42 #include <nic.h> 43 #include < device/pci.h>43 #include <pci_dev_iface.h> 44 44 45 45 #include <ipc/irc.h> … … 190 190 return; 191 191 } 192 193 #include <device/pci.h>194 192 195 193 /** Set PmEn (Power management enable) bit value -
uspace/lib/c/Makefile
ra44424f r99e8fb7b 74 74 generic/device/graph_dev.c \ 75 75 generic/device/nic.c \ 76 generic/device/pci.c \77 76 generic/device/ahci.c \ 78 77 generic/dhcp.c \ -
uspace/lib/drv/generic/remote_pci.c
ra44424f r99e8fb7b 41 41 #include "ddf/driver.h" 42 42 43 typedef enum { 44 IPC_M_CONFIG_SPACE_READ_8, 45 IPC_M_CONFIG_SPACE_READ_16, 46 IPC_M_CONFIG_SPACE_READ_32, 47 48 IPC_M_CONFIG_SPACE_WRITE_8, 49 IPC_M_CONFIG_SPACE_WRITE_16, 50 IPC_M_CONFIG_SPACE_WRITE_32 51 } pci_dev_iface_funcs_t; 52 53 int pci_config_space_read_8(async_sess_t *sess, uint32_t address, uint8_t *val) 54 { 55 sysarg_t res = 0; 56 57 async_exch_t *exch = async_exchange_begin(sess); 58 int rc = async_req_2_1(exch, DEV_IFACE_ID(PCI_DEV_IFACE), 59 IPC_M_CONFIG_SPACE_READ_8, address, &res); 60 async_exchange_end(exch); 61 62 *val = (uint8_t) res; 63 return rc; 64 } 65 66 int pci_config_space_read_16(async_sess_t *sess, uint32_t address, 67 uint16_t *val) 68 { 69 sysarg_t res = 0; 70 71 async_exch_t *exch = async_exchange_begin(sess); 72 int rc = async_req_2_1(exch, DEV_IFACE_ID(PCI_DEV_IFACE), 73 IPC_M_CONFIG_SPACE_READ_16, address, &res); 74 async_exchange_end(exch); 75 76 *val = (uint16_t) res; 77 return rc; 78 } 79 80 int pci_config_space_read_32(async_sess_t *sess, uint32_t address, 81 uint32_t *val) 82 { 83 sysarg_t res = 0; 84 85 async_exch_t *exch = async_exchange_begin(sess); 86 int rc = async_req_2_1(exch, DEV_IFACE_ID(PCI_DEV_IFACE), 87 IPC_M_CONFIG_SPACE_READ_32, address, &res); 88 async_exchange_end(exch); 89 90 *val = (uint32_t) res; 91 return rc; 92 } 93 94 int pci_config_space_write_8(async_sess_t *sess, uint32_t address, uint8_t val) 95 { 96 async_exch_t *exch = async_exchange_begin(sess); 97 int rc = async_req_3_0(exch, DEV_IFACE_ID(PCI_DEV_IFACE), 98 IPC_M_CONFIG_SPACE_WRITE_8, address, val); 99 async_exchange_end(exch); 100 101 return rc; 102 } 103 104 int pci_config_space_write_16(async_sess_t *sess, uint32_t address, 105 uint16_t val) 106 { 107 async_exch_t *exch = async_exchange_begin(sess); 108 int rc = async_req_3_0(exch, DEV_IFACE_ID(PCI_DEV_IFACE), 109 IPC_M_CONFIG_SPACE_WRITE_16, address, val); 110 async_exchange_end(exch); 111 112 return rc; 113 } 114 115 int pci_config_space_write_32(async_sess_t *sess, uint32_t address, 116 uint32_t val) 117 { 118 async_exch_t *exch = async_exchange_begin(sess); 119 int rc = async_req_3_0(exch, DEV_IFACE_ID(PCI_DEV_IFACE), 120 IPC_M_CONFIG_SPACE_WRITE_32, address, val); 121 async_exchange_end(exch); 122 123 return rc; 124 } 125 43 126 static void remote_config_space_read_8(ddf_fun_t *, void *, ipc_callid_t, ipc_call_t *); 44 127 static void remote_config_space_read_16(ddf_fun_t *, void *, ipc_callid_t, ipc_call_t *); -
uspace/lib/drv/include/pci_dev_iface.h
ra44424f r99e8fb7b 40 40 #include "ddf/driver.h" 41 41 42 typedef enum { 43 IPC_M_CONFIG_SPACE_READ_8, 44 IPC_M_CONFIG_SPACE_READ_16, 45 IPC_M_CONFIG_SPACE_READ_32, 42 #define PCI_DEVICE_ID 0x02 46 43 47 IPC_M_CONFIG_SPACE_WRITE_8, 48 IPC_M_CONFIG_SPACE_WRITE_16, 49 IPC_M_CONFIG_SPACE_WRITE_32 50 } pci_dev_iface_funcs_t; 44 extern int pci_config_space_read_8(async_sess_t *, uint32_t, uint8_t *); 45 extern int pci_config_space_read_16(async_sess_t *, uint32_t, uint16_t *); 46 extern int pci_config_space_read_32(async_sess_t *, uint32_t, uint32_t *); 47 48 extern int pci_config_space_write_8(async_sess_t *, uint32_t, uint8_t); 49 extern int pci_config_space_write_16(async_sess_t *, uint32_t, uint16_t); 50 extern int pci_config_space_write_32(async_sess_t *, uint32_t, uint32_t); 51 51 52 52 /** PCI device communication interface. */
Note:
See TracChangeset
for help on using the changeset viewer.