Changeset 9a08e6b in mainline

Timestamp:

2016-05-04T17:39:02Z (9 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

6d87dce

Parents:

5035ba05

Message:

Do not define smc_coherence() macro if not compiling for kernel

Location:

kernel/arch

Files:

• abs32le/include/arch/barrier.h (modified) (1 diff)
• arm32/include/arch/barrier.h (modified) (2 diffs)
• ia32/include/arch/barrier.h (modified) (2 diffs)
• ia64/include/arch/barrier.h (modified) (2 diffs)
• mips32/include/arch/barrier.h (modified) (1 diff)
• ppc32/include/arch/barrier.h (modified) (2 diffs)
• sparc32/include/arch/barrier.h (modified) (1 diff)
• sparc64/include/arch/barrier.h (modified) (2 diffs)

kernel/arch/abs32le/include/arch/barrier.h

@@ -47 +47 @@
 #define write_barrier()
 
+#ifdef KERNEL
+
 #define smc_coherence(addr)
 #define smc_coherence_block(addr, size)
+
+#endif  /* KERNEL*/
 
 #endif

kernel/arch/arm32/include/arch/barrier.h

@@ -97 +97 @@
 #endif
 
+#ifdef KERNEL
+
 /*
  * There are multiple ways ICache can be implemented on ARM machines. Namely
@@ -134 +136 @@
 #endif
 
+#endif  /* KERNEL */
 
 #endif

kernel/arch/ia32/include/arch/barrier.h

@@ -98 +98 @@
 #endif
 
+#ifdef KERNEL
+
 /*
  * On ia32, the hardware takes care about instruction and data cache coherence,
@@ -107 +109 @@
 #define smc_coherence_block(a, l)  write_barrier()
 
+#endif  /* KERNEL */
+
 #endif
 

kernel/arch/ia64/include/arch/barrier.h

@@ -56 +56 @@
         asm volatile (";; sync.i\n" ::: "memory")
 
+#ifdef KERNEL
+
 #define smc_coherence(a)        \
 {                               \
@@ -73 +75 @@
 }
 
+#endif  /* KERNEL */
+
 #endif
 

kernel/arch/mips32/include/arch/barrier.h

@@ -46 +46 @@
 #define write_barrier()  asm volatile ("" ::: "memory")
 
+#ifdef KERNEL
+
 #define smc_coherence(a)
 #define smc_coherence_block(a, l)
+
+#endif  /* KERNEL */
 
 #endif

kernel/arch/ppc32/include/arch/barrier.h

@@ -51 +51 @@
         )
 
+#ifdef KERNEL
+
 #define COHERENCE_INVAL_MIN  4
 
@@ -93 +95 @@
 }
 
+#endif  /* KERNEL */
+
 #endif
 

kernel/arch/sparc32/include/arch/barrier.h

@@ -70 +70 @@
         )
 
+#ifdef KERNEL
 #define smc_coherence(addr)
 #define smc_coherence_block(addr, size)
+#endif  /* KERNEL */
 
 #endif

kernel/arch/sparc64/include/arch/barrier.h

@@ -116 +116 @@
 }
 
-#if defined (US)
+#ifdef KERNEL
+
+#if defined(US)
 
 #define FLUSH_INVAL_MIN  4
@@ -151 +153 @@
 #endif  /* defined(US3) */
 
+#endif  /* KERNEL */
+
 #endif