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  • boot/arch/arm32/include/mm.h

    r0acd339 r9d58539  
    4747/** Describe "section" page table entry (one-level paging with 1 MB sized pages). */
    4848#define PTE_DESCRIPTOR_SECTION  0x02
    49 /** Shift of memory address in section descriptor */
    50 #define PTE_SECTION_SHIFT  20
    5149
    5250/** Page table access rights: user - no access, kernel - read/write. */
    5351#define PTE_AP_USER_NO_KERNEL_RW  0x01
    54 
    55 /** Start of memory mapped I/O area for GTA02 */
    56 #define GTA02_IOMEM_START  0x48000000
    57 /** End of memory mapped I/O area for GTA02 */
    58 #define GTA02_IOMEM_END  0x60000000
    59 
    60 /** Start of ram memory on BBxM */
    61 #define BBXM_RAM_START   0x80000000
    62 /** Start of ram memory on BBxM */
    63 #define BBXM_RAM_END   0xc0000000
    64 
    6552
    6653/* Page table level 0 entry - "section" format is used
     
    7158        unsigned int bufferable : 1;
    7259        unsigned int cacheable : 1;
    73         unsigned int xn : 1;
     60        unsigned int impl_specific : 1;
    7461        unsigned int domain : 4;
    7562        unsigned int should_be_zero_1 : 1;
    76         unsigned int access_permission_0 : 2;
    77         unsigned int tex : 3;
    78         unsigned int access_permission_1 : 2;
    79         unsigned int non_global : 1;
    80         unsigned int should_be_zero_2 : 1;
    81         unsigned int non_secure : 1;
     63        unsigned int access_permission : 2;
     64        unsigned int should_be_zero_2 : 8;
    8265        unsigned int section_base_addr : 12;
    8366} __attribute__((packed)) pte_level0_section_t;
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