Changes in kernel/arch/arm32/include/barrier.h [c124dce3:9d58539] in mainline

File:

• kernel/arch/arm32/include/barrier.h (modified) (1 diff)

kernel/arch/arm32/include/barrier.h

@@ -37 +37 @@
 #define KERN_arm32_BARRIER_H_
 
-#ifdef KERNEL
-#include <arch/cp15.h>
-#else
-#include <libarch/cp15.h>
-#endif
-
+/*
+ * TODO: implement true ARM memory barriers for macros below.
+ */
 #define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
 #define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
 
-#if defined PROCESSOR_ARCH_armv7_a
-/* ARMv7 uses instructions for memory barriers see ARM Architecture reference
- * manual for details:
- * DMB: ch. A8.8.43 page A8-376
- * DSB: ch. A8.8.44 page A8-378
- * See ch. A3.8.3 page A3-148 for details about memory barrier implementation
- * and functionality on armv7 architecture.
- */
-#define memory_barrier()  asm volatile ("dmb" ::: "memory")
-#define read_barrier()    asm volatile ("dsb" ::: "memory")
-#define write_barrier()   asm volatile ("dsb st" ::: "memory")
-#define inst_barrier()    asm volatile ("isb" ::: "memory")
-#elif defined PROCESSOR_ARCH_armv6 | defined KERNEL
-/*
- * ARMv6 introduced user access of the following commands:
- * - Prefetch flush
- * - Data synchronization barrier
- * - Data memory barrier
- * - Clean and prefetch range operations.
- * ARM Architecture Reference Manual version I ch. B.3.2.1 p. B3-4
- */
-/* ARMv6- use system control coprocessor (CP15) for memory barrier instructions.
- * Although at least mcr p15, 0, r0, c7, c10, 4 is mentioned in earlier archs,
- * CP15 implementation is mandatory only for armv6+.
- */
-#define memory_barrier()  CP15DMB_write(0)
-#define read_barrier()    CP15DSB_write(0)
-#define write_barrier()   read_barrier()
-#define inst_barrier()    CP15ISB_write(0)
-#else
-/* Older manuals mention syscalls as a way to implement cache coherency and
- * barriers. See for example ARM Architecture Reference Manual Version D
- * chapter 2.7.4 Prefetching and self-modifying code (p. A2-28)
- */
-// TODO implement on per PROCESSOR basis or via syscalls
 #define memory_barrier()  asm volatile ("" ::: "memory")
 #define read_barrier()    asm volatile ("" ::: "memory")
 #define write_barrier()   asm volatile ("" ::: "memory")
-#define inst_barrier()    asm volatile ("" ::: "memory")
-#endif
 
-/*
- * There are multiple ways ICache can be implemented on ARM machines. Namely
- * PIPT, VIPT, and ASID and VMID tagged VIVT (see ARM Architecture Reference
- * Manual B3.11.2 (p. 1383).  However, CortexA8 Manual states: "For maximum
- * compatibility across processors, ARM recommends that operating systems target
- * the ARMv7 base architecture that uses ASID-tagged VIVT instruction caches,
- * and do not assume the presence of the IVIPT extension. Software that relies
- * on the IVIPT extension might fail in an unpredictable way on an ARMv7
- * implementation that does not include the IVIPT extension." (7.2.6 p. 245).
- * Only PIPT invalidates cache for all VA aliases if one block is invalidated.
- *
- * @note: Supporting ASID and VMID tagged VIVT may need to add ICache
- * maintenance to other places than just smc.
- */
-
-#if defined PROCESSOR_ARCH_armv7_a | defined PROCESSOR_ARCH_armv6 | defined KERNEL
-/* Available on all supported arms,
- * invalidates entire ICache so the written value does not matter. */
-//TODO might be PL1 only on armv5-
-#define smc_coherence(a) \
-do { \
-        DCCMVAU_write((uint32_t)(a));  /* Flush changed memory */\
-        write_barrier();               /* Wait for completion */\
-        ICIALLU_write(0);              /* Flush ICache */\
-        inst_barrier();                /* Wait for Inst refetch */\
-} while (0)
-/* @note: Cache type register is not available in uspace. We would need
- * to export the cache line value, or use syscall for uspace smc_coherence */
-#define smc_coherence_block(a, l) \
-do { \
-        for (uintptr_t addr = (uintptr_t)a; addr < (uintptr_t)a + l; addr += 4)\
-                smc_coherence(addr); \
-} while (0)
-#else
 #define smc_coherence(a)
 #define smc_coherence_block(a, l)
-#endif
-
 
 #endif