Changes in kernel/arch/arm32/src/cpu/cpu.c [8316547f:9d58539] in mainline

File:

• kernel/arch/arm32/src/cpu/cpu.c (modified) (3 diffs)

kernel/arch/arm32/src/cpu/cpu.c

@@ -44 +44 @@
 /** Implementators (vendor) names */
 static const char *imp_data[] = {
-        "?",                                     /* IMP_DATA_START_OFFSET */
-        "ARM Limited",                           /* 0x41 */
-        "", "",                                  /* 0x42 - 0x43 */
-        "Digital Equipment Corporation",         /* 0x44 */
-        "", "", "", "", "", "", "", "",          /* 0x45 - 0x4c */
-        "Motorola, Freescale Semicondutor Inc.", /* 0x4d */
-        "", "", "",                              /* 0x4e - 0x50 */
-        "Qualcomm Inc.",                         /* 0x51 */
-        "", "", "", "",                          /* 0x52 - 0x55 */
-        "Marvell Semiconductor",                 /* 0x56 */
-        "", "", "", "", "", "", "", "", "", "",  /* 0x57 - 0x60 */
-        "", "", "", "", "", "", "", "",          /* 0x61 - 0x68 */
-        "Intel Corporation"                      /* 0x69 */
+        "?",                                    /* IMP_DATA_START_OFFSET */
+        "ARM Ltd",                              /* 0x41 */
+        "",                                     /* 0x42 */
+        "",                                     /* 0x43 */
+        "Digital Equipment Corporation",        /* 0x44 */
+        "", "", "", "", "", "", "", "", "", "", /* 0x45 - 0x4e */
+        "", "", "", "", "", "", "", "", "", "", /* 0x4f - 0x58 */
+        "", "", "", "", "", "", "", "", "", "", /* 0x59 - 0x62 */
+        "", "", "", "", "", "",                 /* 0x63 - 0x68 */
+        "Intel Corporation"                     /* 0x69 */
 };
 
@@ -97 +94 @@
 }
 
-/** Enables unaligned access and caching for armv6+ */
+/** Does nothing on ARM. */
 void cpu_arch_init(void)
 {
-#if defined(PROCESSOR_armv7_a) | defined(PROCESSOR_armv6)
-        uint32_t control_reg = 0;
-        asm volatile (
-                "mrc p15, 0, %[control_reg], c1, c0"
-                : [control_reg] "=r" (control_reg)
-        );
-        
-        /* Turn off tex remap, RAZ ignores writes prior to armv7 */
-        control_reg &= ~CP15_R1_TEX_REMAP_EN;
-        /* Turn off accessed flag, RAZ ignores writes prior to armv7 */
-        control_reg &= ~(CP15_R1_ACCESS_FLAG_EN | CP15_R1_HW_ACCESS_FLAG_EN);
-        /* Enable unaligned access, RAZ ignores writes prior to armv6
-         * switchable on armv6, RAO ignores writes on armv7,
-         * see ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
-         * L.3.1 (p. 2456) */
-        control_reg |= CP15_R1_UNALIGNED_EN;
-        /* Disable alignment checks, this turns unaligned access to undefined,
-         * unless U bit is set. */
-        control_reg &= ~CP15_R1_ALIGN_CHECK_EN;
-        /* Enable caching, On arm prior to armv7 there is only one level
-         * of caches. Data cache is coherent.
-         * "This means that the behavior of accesses from the same observer to
-         * different VAs, that are translated to the same PA
-         * with the same memory attributes, is fully coherent."
-         *    ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition
-         *    B3.11.1 (p. 1383)
-         * ICache coherency is elaborate on in barrier.h.
-         * We are safe to turn these on.
-         */
-        control_reg |= CP15_R1_CACHE_EN | CP15_R1_INST_CACHE_EN;
-        
-        asm volatile (
-                "mcr p15, 0, %[control_reg], c1, c0"
-                :: [control_reg] "r" (control_reg)
-        );
-#endif
 }
 
 /** Retrieves processor identification and stores it to #CPU.arch */
-void cpu_identify(void)
+void cpu_identify(void) 
 {
         arch_cpu_identify(&CPU->arch);
@@ -151 +112 @@
         cpu_arch_t * cpu_arch = &m->arch;
 
-        const unsigned imp_offset = cpu_arch->imp_num - IMP_DATA_START_OFFSET;
-
-        if (imp_offset < imp_data_length) {
+        if ((cpu_arch->imp_num) > 0 &&
+            (cpu_arch->imp_num < (imp_data_length + IMP_DATA_START_OFFSET))) {
                 vendor = imp_data[cpu_arch->imp_num - IMP_DATA_START_OFFSET];
         }
 
-        // TODO CPUs with arch_num == 0xf use CPUID scheme for identification
-        if (cpu_arch->arch_num < arch_data_length) {
+        if ((cpu_arch->arch_num) > 0 &&
+            (cpu_arch->arch_num < arch_data_length)) {
                 architecture = arch_data[cpu_arch->arch_num];
         }