Changes in kernel/arch/arm32/src/mm/tlb.c [f834cc32:9d58539] in mainline

File:

• kernel/arch/arm32/src/mm/tlb.c (modified) (5 diffs)

kernel/arch/arm32/src/mm/tlb.c

@@ -37 +37 @@
 #include <arch/mm/asid.h>
 #include <arch/asm.h>
-#include <arch/cp15.h>
 #include <typedefs.h>
 #include <arch/mm/page.h>
-#include <arch/cache.h>
 
 /** Invalidate all entries in TLB.
@@ -48 +46 @@
 void tlb_invalidate_all(void)
 {
-        TLBIALL_write(0);
-        /*
-         * "A TLB maintenance operation is only guaranteed to be complete after
-         * the execution of a DSB instruction."
-         * "An ISB instruction, or a return from an exception, causes the
-         * effect of all completed TLB maintenance operations that appear in
-         * program order before the ISB or return from exception to be visible
-         * to all subsequent instructions, including the instruction fetches
-         * for those instructions."
-         * ARM Architecture reference Manual ch. B3.10.1 p. B3-1374 B3-1375
-         */
-        read_barrier();
-        inst_barrier();
+        asm volatile (
+                "eor r1, r1\n"
+                "mcr p15, 0, r1, c8, c7, 0\n"
+                ::: "r1"
+        );
 }
 
@@ -70 +60 @@
 {
         tlb_invalidate_all();
-        // TODO: why not TLBIASID_write(asid) ?
 }
 
@@ -76 +65 @@
  *
  * @param page Virtual adress of the page
- */
+ */ 
 static inline void invalidate_page(uintptr_t page)
 {
-#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
-        if (TLBTR_read() & TLBTR_SEP_FLAG) {
-                ITLBIMVA_write(page);
-                DTLBIMVA_write(page);
-        } else {
-                TLBIMVA_write(page);
-        }
-#elif defined(PROCESSOR_arm920t)
-        ITLBIMVA_write(page);
-        DTLBIMVA_write(page);
-#elif defined(PROCESSOR_arm926ej_s)
-        TLBIMVA_write(page);
-#else
-#error Unknown TLB type
-#endif
-
-        /*
-         * "A TLB maintenance operation is only guaranteed to be complete after
-         * the execution of a DSB instruction."
-         * "An ISB instruction, or a return from an exception, causes the
-         * effect of all completed TLB maintenance operations that appear in
-         * program order before the ISB or return from exception to be visible
-         * to all subsequent instructions, including the instruction fetches
-         * for those instructions."
-         * ARM Architecture reference Manual ch. B3.10.1 p. B3-1374 B3-1375
-         */
-        read_barrier();
-        inst_barrier();
+        asm volatile (
+                "mcr p15, 0, %[page], c8, c7, 1\n"
+                :: [page] "r" (page)
+        );
 }
 
@@ -118 +83 @@
 void tlb_invalidate_pages(asid_t asid __attribute__((unused)), uintptr_t page, size_t cnt)
 {
-        for (unsigned i = 0; i < cnt; i++)
+        unsigned int i;
+
+        for (i = 0; i < cnt; i++)
                 invalidate_page(page + i * PAGE_SIZE);
 }