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  • kernel/arch/mips32/src/exception.c

    r7be6379 r9d58539  
    165165static void interrupt_exception(unsigned int n, istate_t *istate)
    166166{
    167         uint32_t ip;
    168         uint32_t im;
    169 
    170167        /* Decode interrupt number and process the interrupt */
    171         ip = (cp0_cause_read() & cp0_cause_ip_mask) >> cp0_cause_ip_shift;
    172         im = (cp0_status_read() & cp0_status_im_mask) >> cp0_status_im_shift;
     168        uint32_t cause = (cp0_cause_read() >> 8) & 0xff;
    173169       
    174170        unsigned int i;
    175171        for (i = 0; i < 8; i++) {
    176 
    177                 /*
    178                  * The interrupt could only occur if it is unmasked in the
    179                  * status register. On the other hand, an interrupt can be
    180                  * apparently pending even if it is masked, so we need to
    181                  * check both the masked and pending interrupts.
    182                  */
    183                 if (im & ip & (1 << i)) {
     172                if (cause & (1 << i)) {
    184173                        irq_t *irq = irq_dispatch_and_lock(i);
    185174                        if (irq) {
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