Changes in kernel/arch/ppc32/src/exception.S [b66cc97:9d58539] in mainline
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kernel/arch/ppc32/src/exception.S
rb66cc97 r9d58539 27 27 # 28 28 29 #include <abi/asmtool.h>30 29 #include <arch/asm/regname.h> 31 30 #include <arch/msr.h> 32 31 #include <arch/mm/page.h> 33 #include <arch/istate_struct.h>34 #include <arch/stack.h>35 #include <align.h>36 32 37 33 .section K_UNMAPPED_TEXT_START, "ax" … … 46 42 mtsprg2 sp 47 43 48 # check whether the previous mode was user or kernel 49 50 mfsrr1 sp # use sp as a temporary register to hold SRR1 51 andi. sp, sp, MSR_PR 44 # check whether SP is in kernel 45 46 andis. sp, sp, 0x8000 52 47 bne 1f 53 # previous mode was kernel 48 49 # stack is in user-space 50 51 mfsprg0 sp 52 53 b 2f 54 55 1: 56 57 # stack is in kernel 54 58 55 59 mfsprg2 sp 56 60 subis sp, sp, 0x8000 57 b 2f 58 59 1: 60 # previous mode was user 61 62 mfsprg0 sp 61 63 62 2: 64 63 65 subi sp, sp, ALIGN_UP(ISTATE_SIZE, STACK_ALIGNMENT)66 stw r0, ISTATE_OFFSET_R0(sp)67 stw r2, ISTATE_OFFSET_R2(sp)68 stw r3, ISTATE_OFFSET_R3(sp)69 stw r4, ISTATE_OFFSET_R4(sp)70 stw r5, ISTATE_OFFSET_R5(sp)71 stw r6, ISTATE_OFFSET_R6(sp)72 stw r7, ISTATE_OFFSET_R7(sp)73 stw r8, ISTATE_OFFSET_R8(sp)74 stw r9, ISTATE_OFFSET_R9(sp)75 stw r10, ISTATE_OFFSET_R10(sp)76 stw r11, ISTATE_OFFSET_R11(sp)77 stw r13, ISTATE_OFFSET_R13(sp)78 stw r14, ISTATE_OFFSET_R14(sp)79 stw r15, ISTATE_OFFSET_R15(sp)80 stw r16, ISTATE_OFFSET_R16(sp)81 stw r17, ISTATE_OFFSET_R17(sp)82 stw r18, ISTATE_OFFSET_R18(sp)83 stw r19, ISTATE_OFFSET_R19(sp)84 stw r20, ISTATE_OFFSET_R20(sp)85 stw r21, ISTATE_OFFSET_R21(sp)86 stw r22, ISTATE_OFFSET_R22(sp)87 stw r23, ISTATE_OFFSET_R23(sp)88 stw r24, ISTATE_OFFSET_R24(sp)89 stw r25, ISTATE_OFFSET_R25(sp)90 stw r26, ISTATE_OFFSET_R26(sp)91 stw r27, ISTATE_OFFSET_R27(sp)92 stw r28, ISTATE_OFFSET_R28(sp)93 stw r29, ISTATE_OFFSET_R29(sp)94 stw r30, ISTATE_OFFSET_R30(sp)95 stw r31, ISTATE_OFFSET_R31(sp)96 97 stw r12, ISTATE_OFFSET_CR(sp)64 subi sp, sp, 164 65 stw r0, 8(sp) 66 stw r2, 12(sp) 67 stw r3, 16(sp) 68 stw r4, 20(sp) 69 stw r5, 24(sp) 70 stw r6, 28(sp) 71 stw r7, 32(sp) 72 stw r8, 36(sp) 73 stw r9, 40(sp) 74 stw r10, 44(sp) 75 stw r11, 48(sp) 76 stw r13, 52(sp) 77 stw r14, 56(sp) 78 stw r15, 60(sp) 79 stw r16, 64(sp) 80 stw r17, 68(sp) 81 stw r18, 72(sp) 82 stw r19, 76(sp) 83 stw r20, 80(sp) 84 stw r21, 84(sp) 85 stw r22, 88(sp) 86 stw r23, 92(sp) 87 stw r24, 96(sp) 88 stw r25, 100(sp) 89 stw r26, 104(sp) 90 stw r27, 108(sp) 91 stw r28, 112(sp) 92 stw r29, 116(sp) 93 stw r30, 120(sp) 94 stw r31, 124(sp) 95 96 stw r12, 128(sp) 98 97 99 98 mfsrr0 r12 100 stw r12, ISTATE_OFFSET_PC(sp)99 stw r12, 132(sp) 101 100 102 101 mfsrr1 r12 103 stw r12, ISTATE_OFFSET_SRR1(sp)102 stw r12, 136(sp) 104 103 105 104 mflr r12 106 stw r12, ISTATE_OFFSET_LR(sp)105 stw r12, 140(sp) 107 106 108 107 mfctr r12 109 stw r12, ISTATE_OFFSET_CTR(sp)108 stw r12, 144(sp) 110 109 111 110 mfxer r12 112 stw r12, ISTATE_OFFSET_XER(sp)111 stw r12, 148(sp) 113 112 114 113 mfdar r12 115 stw r12, ISTATE_OFFSET_DAR(sp)114 stw r12, 152(sp) 116 115 117 116 mfsprg1 r12 118 stw r12, ISTATE_OFFSET_R12(sp)117 stw r12, 156(sp) 119 118 120 119 mfsprg2 r12 121 stw r12, ISTATE_OFFSET_SP(sp) 122 123 li r12, 0 124 stw r12, ISTATE_OFFSET_LR_FRAME(sp) 125 stw r12, ISTATE_OFFSET_SP_FRAME(sp) 120 stw r12, 160(sp) 126 121 .endm 127 122 128 123 .org 0x100 129 SYMBOL(exc_system_reset) 124 .global exc_system_reset 125 exc_system_reset: 130 126 CONTEXT_STORE 131 127 … … 134 130 135 131 .org 0x200 136 SYMBOL(exc_machine_check) 132 .global exc_machine_check 133 exc_machine_check: 137 134 CONTEXT_STORE 138 135 … … 141 138 142 139 .org 0x300 143 SYMBOL(exc_data_storage) 140 .global exc_data_storage 141 exc_data_storage: 144 142 CONTEXT_STORE 145 143 … … 148 146 149 147 .org 0x400 150 SYMBOL(exc_instruction_storage) 148 .global exc_instruction_storage 149 exc_instruction_storage: 151 150 CONTEXT_STORE 152 151 … … 155 154 156 155 .org 0x500 157 SYMBOL(exc_external) 156 .global exc_external 157 exc_external: 158 158 CONTEXT_STORE 159 159 … … 162 162 163 163 .org 0x600 164 SYMBOL(exc_alignment) 164 .global exc_alignment 165 exc_alignment: 165 166 CONTEXT_STORE 166 167 … … 169 170 170 171 .org 0x700 171 SYMBOL(exc_program) 172 .global exc_program 173 exc_program: 172 174 CONTEXT_STORE 173 175 … … 176 178 177 179 .org 0x800 178 SYMBOL(exc_fp_unavailable) 180 .global exc_fp_unavailable 181 exc_fp_unavailable: 179 182 CONTEXT_STORE 180 183 … … 183 186 184 187 .org 0x900 185 SYMBOL(exc_decrementer) 188 .global exc_decrementer 189 exc_decrementer: 186 190 CONTEXT_STORE 187 191 … … 190 194 191 195 .org 0xa00 192 SYMBOL(exc_reserved0) 196 .global exc_reserved0 197 exc_reserved0: 193 198 CONTEXT_STORE 194 199 … … 197 202 198 203 .org 0xb00 199 SYMBOL(exc_reserved1) 204 .global exc_reserved1 205 exc_reserved1: 200 206 CONTEXT_STORE 201 207 … … 204 210 205 211 .org 0xc00 206 SYMBOL(exc_syscall) 212 .global exc_syscall 213 exc_syscall: 207 214 CONTEXT_STORE 208 215 … … 210 217 211 218 .org 0xd00 212 SYMBOL(exc_trace) 219 .global exc_trace 220 exc_trace: 213 221 CONTEXT_STORE 214 222 … … 217 225 218 226 .org 0x1000 219 SYMBOL(exc_itlb_miss) 227 .global exc_itlb_miss 228 exc_itlb_miss: 220 229 CONTEXT_STORE 221 230 … … 224 233 225 234 .org 0x1100 226 SYMBOL(exc_dtlb_miss_load) 235 .global exc_dtlb_miss_load 236 exc_dtlb_miss_load: 227 237 CONTEXT_STORE 228 238 … … 231 241 232 242 .org 0x1200 233 SYMBOL(exc_dtlb_miss_store) 243 .global exc_dtlb_miss_store 244 exc_dtlb_miss_store: 234 245 CONTEXT_STORE 235 246 … … 239 250 .org 0x4000 240 251 jump_to_kernel: 241 mfsrr1 r5242 andi. r5, r5, MSR_PR243 bne 1f244 # Previous mode was kernel.245 # We can construct a proper frame linkage.246 247 mfsrr0 r12248 stw r12, ISTATE_OFFSET_LR_FRAME(sp)249 mfsprg2 r12250 stw r12, ISTATE_OFFSET_SP_FRAME(sp)251 1:252 253 252 lis r12, iret@ha 254 253 addi r12, r12, iret@l 255 254 mtlr r12 256 255 257 256 lis r12, exc_dispatch@ha 258 257 addi r12, r12, exc_dispatch@l 259 258 mtsrr0 r12 260 259 261 260 mfmsr r12 262 mfsrr1 r5 263 andi. r5, r5, MSR_FP 264 or r12, r12, r5 # Propagate MSR_FP from SRR1 to MSR 265 ori r12, r12, (MSR_IR | MSR_DR) 261 ori r12, r12, (MSR_IR | MSR_DR)@l 266 262 mtsrr1 r12 267 263 268 264 addis sp, sp, 0x8000 269 265 mr r4, sp 266 addi r4, r4, 8 270 267 271 268 rfi … … 279 276 addi r12, r12, iret_syscall@l 280 277 mtlr r12 281 282 mfsrr1 r0 283 andi. r0, r0, MSR_FP 278 284 279 mfmsr r12 285 or r12, r12, r0 # Propagate MSR_FP from SRR1 to MSR 286 ori r12, r12, (MSR_IR | MSR_DR | MSR_EE) 280 ori r12, r12, (MSR_IR | MSR_DR)@l 287 281 mtsrr1 r12 288 282
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