Changeset 9ea8a7ca in mainline

Timestamp:

2006-02-02T12:47:40Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

758e065

Parents:

4e147a6

Message:

mips32 is not supposed to allocate page table.
This is done by the generic code now.
Remove PTL0 pointer as it is not needed.

Remove GET_PTL0_ADDRESS from kernel.

Update sparc64 comments in barrier.h.

Files:

• arch/amd64/include/mm/page.h (modified) (1 diff)
• arch/ia32/include/mm/page.h (modified) (1 diff)
• arch/mips32/include/mm/page.h (modified) (2 diffs)
• arch/mips32/src/mm/page.c (modified) (1 diff)
• arch/ppc32/include/mm/page.h (modified) (1 diff)
• arch/sparc64/include/barrier.h (modified) (1 diff)
• genarch/include/mm/page_pt.h (modified) (1 diff)

arch/amd64/include/mm/page.h

@@ -51 +51 @@
 #define PTL3_INDEX_ARCH(vaddr)  (((vaddr)>>12)&0x1ff)
 
-#define GET_PTL0_ADDRESS_ARCH()                 ((pte_t *) read_cr3())
 #define GET_PTL1_ADDRESS_ARCH(ptl0, i)          ((pte_t *) ((((__u64) ((pte_t *)(ptl0))[(i)].addr_12_31)<<12) | (((__u64) ((pte_t *)(ptl0))[(i)].addr_32_51)<<32 )))
 #define GET_PTL2_ADDRESS_ARCH(ptl1, i)          ((pte_t *) ((((__u64) ((pte_t *)(ptl1))[(i)].addr_12_31)<<12) | (((__u64) ((pte_t *)(ptl1))[(i)].addr_32_51)<<32 )))

arch/ia32/include/mm/page.h

@@ -49 +49 @@
 #define PTL3_INDEX_ARCH(vaddr)  (((vaddr)>>12)&0x3ff)
 
-#define GET_PTL0_ADDRESS_ARCH()                 ((pte_t *) read_cr3())
 #define GET_PTL1_ADDRESS_ARCH(ptl0, i)          ((pte_t *)((((pte_t *)(ptl0))[(i)].frame_address)<<12))
 #define GET_PTL2_ADDRESS_ARCH(ptl1, i)          (ptl1)

arch/mips32/include/mm/page.h

@@ -60 +60 @@
 #define PTL3_INDEX_ARCH(vaddr)  (((vaddr)>>14)&0x3fff)
 
-#define GET_PTL0_ADDRESS_ARCH()                 (PTL0)
-#define SET_PTL0_ADDRESS_ARCH(ptl0)             (PTL0 = (pte_t *)(ptl0))
+#define SET_PTL0_ADDRESS_ARCH(ptl0)
 
 #define GET_PTL1_ADDRESS_ARCH(ptl0, i)          (((pte_t *)(ptl0))[(i)].lo.pfn<<12)
@@ -116 +115 @@
 extern void page_arch_init(void);
 
-extern pte_t *PTL0;
-
 #endif /* __ASM__ */
 

arch/mips32/src/mm/page.c

@@ -29 +29 @@
 #include <arch/mm/page.h>
 #include <genarch/mm/page_pt.h>
-#include <arch/mm/frame.h>
-#include <mm/frame.h>
 #include <mm/page.h>
-#include <arch/types.h>
-#include <memstr.h>
-
-pte_t *PTL0 = NULL;
 
 void page_arch_init(void)
 {
-        __address ptl0;
-
         page_operations = &page_pt_operations;
-        
-        ptl0 = frame_alloc(FRAME_KA | FRAME_PANIC, ONE_FRAME, NULL);
-        memsetb(ptl0, FRAME_SIZE, 0);
-        
-        SET_PTL0_ADDRESS(KA2PA(ptl0));
 }

arch/ppc32/include/mm/page.h

@@ -44 +44 @@
 #define PTL3_INDEX_ARCH(vaddr)          0
 
-#define GET_PTL0_ADDRESS_ARCH()         0
 #define SET_PTL0_ADDRESS_ARCH(ptl0)
 

arch/sparc64/include/barrier.h

@@ -40 +40 @@
 #define write_barrier()
 
-/** Flush Instruction Memory. */
+/** Flush Instruction Memory instruction. */
 static inline void flush(void)
 {
         /*
-         * The FLUSH instruction takes address parameter,
-         * but JPS1 implementations are free to ignore it.
-         * The only requirement is that it is a valid address
-         * as it is passed to D-MMU.
+         * The FLUSH instruction takes address parameter.
+         * As such, it may trap if the address is not found in DTLB.
+         * However, JPS1 implementations are free to ignore the trap.
          */
-        __asm__ volatile ("flush %sp\n");       /* %sp is guaranteed to reference mapped memory */
+        __asm__ volatile ("flush %sp\n");
 }
 
+/** Memory Barrier instruction. */
 static inline void membar(void)
 {

genarch/include/mm/page_pt.h

@@ -49 +49 @@
 #define PTL3_INDEX(vaddr)               PTL3_INDEX_ARCH(vaddr)
 
-#define GET_PTL0_ADDRESS()              GET_PTL0_ADDRESS_ARCH()
 #define SET_PTL0_ADDRESS(ptl0)          SET_PTL0_ADDRESS_ARCH(ptl0)