Changes in kernel/arch/ppc32/src/mm/tlb.c [8f80c77:a000878c] in mainline
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kernel/arch/ppc32/src/mm/tlb.c
r8f80c77 ra000878c 45 45 46 46 static unsigned int seed = 10; 47 static unsigned int seed_real 48 __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42; 47 static unsigned int seed_real __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42; 48 49 49 50 50 /** Try to find PTE for faulting address 51 51 * 52 * @param as Address space. 53 * @param lock Lock/unlock the address space. 54 * @param badvaddr Faulting virtual address. 55 * @param access Access mode that caused the fault. 56 * @param istate Pointer to interrupted state. 57 * @param pfrc Pointer to variable where as_page_fault() return code 58 * will be stored. 59 * 60 * @return PTE on success, NULL otherwise. 61 * 62 */ 63 static pte_t *find_mapping_and_check(as_t *as, uintptr_t badvaddr, int access, 52 * Try to find PTE for faulting address. 53 * The as->lock must be held on entry to this function 54 * if lock is true. 55 * 56 * @param as Address space. 57 * @param lock Lock/unlock the address space. 58 * @param badvaddr Faulting virtual address. 59 * @param access Access mode that caused the fault. 60 * @param istate Pointer to interrupted state. 61 * @param pfrc Pointer to variable where as_page_fault() return code 62 * will be stored. 63 * @return PTE on success, NULL otherwise. 64 * 65 */ 66 static pte_t * 67 find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access, 64 68 istate_t *istate, int *pfrc) 65 69 { 66 ASSERT(mutex_locked(&as->lock));67 68 70 /* 69 71 * Check if the mapping exists in page tables. 70 */ 72 */ 71 73 pte_t *pte = page_mapping_find(as, badvaddr); 72 74 if ((pte) && (pte->present)) { … … 77 79 return pte; 78 80 } else { 81 int rc; 82 79 83 /* 80 84 * Mapping not found in page tables. 81 85 * Resort to higher-level page fault handler. 82 86 */ 83 page_table_unlock(as, true); 84 85 int rc = as_page_fault(badvaddr, access, istate); 86 switch (rc) { 87 page_table_unlock(as, lock); 88 switch (rc = as_page_fault(badvaddr, access, istate)) { 87 89 case AS_PF_OK: 88 90 /* … … 90 92 * The mapping ought to be in place. 91 93 */ 92 page_table_lock(as, true);94 page_table_lock(as, lock); 93 95 pte = page_mapping_find(as, badvaddr); 94 96 ASSERT((pte) && (pte->present)); … … 96 98 return pte; 97 99 case AS_PF_DEFER: 98 page_table_lock(as, true);100 page_table_lock(as, lock); 99 101 *pfrc = rc; 100 102 return NULL; 101 103 case AS_PF_FAULT: 102 page_table_lock(as, true);104 page_table_lock(as, lock); 103 105 *pfrc = rc; 104 106 return NULL; 105 107 default: 106 108 panic("Unexpected rc (%d).", rc); 107 } 108 } 109 } 109 } 110 } 111 } 112 110 113 111 114 static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate) … … 120 123 } 121 124 125 122 126 static void pht_insert(const uintptr_t vaddr, const pte_t *pte) 123 127 { … … 125 129 uint32_t api = (vaddr >> 22) & 0x3f; 126 130 127 uint32_t vsid = sr_get(vaddr); 128 uint32_t sdr1 = sdr1_get(); 129 130 // FIXME: compute size of PHT exactly 131 uint32_t vsid; 132 asm volatile ( 133 "mfsrin %0, %1\n" 134 : "=r" (vsid) 135 : "r" (vaddr) 136 ); 137 138 uint32_t sdr1; 139 asm volatile ( 140 "mfsdr1 %0\n" 141 : "=r" (sdr1) 142 ); 131 143 phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); 132 144 … … 203 215 } 204 216 217 205 218 /** Process Instruction/Data Storage Exception 206 219 * … … 211 224 void pht_refill(int n, istate_t *istate) 212 225 { 213 as_t *as = (AS == NULL) ? AS_KERNEL : AS;214 226 uintptr_t badvaddr; 227 pte_t *pte; 228 int pfrc; 229 as_t *as; 230 bool lock; 231 232 if (AS == NULL) { 233 as = AS_KERNEL; 234 lock = false; 235 } else { 236 as = AS; 237 lock = true; 238 } 215 239 216 240 if (n == VECTOR_DATA_STORAGE) … … 218 242 else 219 243 badvaddr = istate->pc; 220 221 page_table_lock(as, true); 222 223 int pfrc; 224 pte_t *pte = find_mapping_and_check(as, badvaddr, 244 245 page_table_lock(as, lock); 246 247 pte = find_mapping_and_check(as, lock, badvaddr, 225 248 PF_ACCESS_READ /* FIXME */, istate, &pfrc); 226 227 249 if (!pte) { 228 250 switch (pfrc) { … … 235 257 * or copy_to_uspace(). 236 258 */ 237 page_table_unlock(as, true);259 page_table_unlock(as, lock); 238 260 return; 239 261 default: … … 242 264 } 243 265 244 /* Record access to PTE */ 245 pte->accessed = 1; 266 pte->accessed = 1; /* Record access to PTE */ 246 267 pht_insert(badvaddr, pte); 247 268 248 page_table_unlock(as, true);269 page_table_unlock(as, lock); 249 270 return; 250 271 251 272 fail: 252 page_table_unlock(as, true);273 page_table_unlock(as, lock); 253 274 pht_refill_fail(badvaddr, istate); 254 275 } 276 255 277 256 278 /** Process Instruction/Data Storage Exception in Real Mode … … 269 291 badvaddr = istate->pc; 270 292 271 uint32_t physmem = physmem_top(); 293 uint32_t physmem; 294 asm volatile ( 295 "mfsprg3 %0\n" 296 : "=r" (physmem) 297 ); 272 298 273 299 if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) … … 277 303 uint32_t api = (badvaddr >> 22) & 0x3f; 278 304 279 uint32_t vsid = sr_get(badvaddr); 280 uint32_t sdr1 = sdr1_get(); 281 282 // FIXME: compute size of PHT exactly 305 uint32_t vsid; 306 asm volatile ( 307 "mfsrin %0, %1\n" 308 : "=r" (vsid) 309 : "r" (badvaddr) 310 ); 311 312 uint32_t sdr1; 313 asm volatile ( 314 "mfsdr1 %0\n" 315 : "=r" (sdr1) 316 ); 283 317 phte_t *phte_real = (phte_t *) (sdr1 & 0xffff0000); 284 318 … … 362 396 } 363 397 398 364 399 /** Process ITLB/DTLB Miss Exception in Real Mode 365 400 * … … 369 404 { 370 405 uint32_t badvaddr = tlbmiss & 0xfffffffc; 371 uint32_t physmem = physmem_top(); 406 407 uint32_t physmem; 408 asm volatile ( 409 "mfsprg3 %0\n" 410 : "=r" (physmem) 411 ); 372 412 373 413 if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) … … 380 420 uint32_t index = 0; 381 421 asm volatile ( 382 "mtspr 981, %[ptehi]\n" 383 "mtspr 982, %[ptelo]\n" 384 "tlbld %[index]\n" 385 "tlbli %[index]\n" 386 : [index] "=r" (index) 387 : [ptehi] "r" (ptehi), 388 [ptelo] "r" (ptelo) 389 ); 390 } 422 "mtspr 981, %0\n" 423 "mtspr 982, %1\n" 424 "tlbld %2\n" 425 "tlbli %2\n" 426 : "=r" (index) 427 : "r" (ptehi), 428 "r" (ptelo) 429 ); 430 } 431 391 432 392 433 void tlb_arch_init(void) … … 395 436 } 396 437 438 397 439 void tlb_invalidate_all(void) 398 440 { 399 441 uint32_t index; 400 401 asm volatile ( 402 "li %[index], 0\n" 442 asm volatile ( 443 "li %0, 0\n" 403 444 "sync\n" 404 445 405 446 ".rept 64\n" 406 " tlbie %[index]\n"407 " addi %[index], %[index], 0x1000\n"447 "tlbie %0\n" 448 "addi %0, %0, 0x1000\n" 408 449 ".endr\n" 409 450 … … 411 452 "tlbsync\n" 412 453 "sync\n" 413 : [index] "=r" (index) 414 ); 415 } 454 : "=r" (index) 455 ); 456 } 457 416 458 417 459 void tlb_invalidate_asid(asid_t asid) 418 460 { 419 uint32_t sdr1 = sdr1_get(); 420 421 // FIXME: compute size of PHT exactly 461 uint32_t sdr1; 462 asm volatile ( 463 "mfsdr1 %0\n" 464 : "=r" (sdr1) 465 ); 422 466 phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); 423 467 424 size_t i;468 uint32_t i; 425 469 for (i = 0; i < 8192; i++) { 426 470 if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) && … … 428 472 phte[i].v = 0; 429 473 } 430 431 474 tlb_invalidate_all(); 432 475 } 476 433 477 434 478 void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt) … … 438 482 } 439 483 484 440 485 #define PRINT_BAT(name, ureg, lreg) \ 441 486 asm volatile ( \ 442 "mfspr %[upper], " #ureg "\n" \ 443 "mfspr %[lower], " #lreg "\n" \ 444 : [upper] "=r" (upper), \ 445 [lower] "=r" (lower) \ 487 "mfspr %0," #ureg "\n" \ 488 "mfspr %1," #lreg "\n" \ 489 : "=r" (upper), "=r" (lower) \ 446 490 ); \ 447 \448 491 mask = (upper & 0x1ffc) >> 2; \ 449 492 if (upper & 3) { \ 450 493 uint32_t tmp = mask; \ 451 494 length = 128; \ 452 \453 495 while (tmp) { \ 454 496 if ((tmp & 1) == 0) { \ … … 461 503 } else \ 462 504 length = 0; \ 463 \464 505 printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \ 465 506 sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \ … … 474 515 475 516 for (sr = 0; sr < 16; sr++) { 476 uint32_t vsid = sr_get(sr << 28); 477 517 uint32_t vsid; 518 asm volatile ( 519 "mfsrin %0, %1\n" 520 : "=r" (vsid) 521 : "r" (sr << 28) 522 ); 478 523 printf("sr[%02u]: vsid=%.*p (asid=%u)%s%s\n", sr, 479 524 sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4,
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