Changeset a016b63 in mainline


Ignore:
Timestamp:
2005-10-10T20:26:02Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
a783ca4
Parents:
e0cdb7b6
Message:

Small improvement in pte_t type definition.

Location:
arch
Files:
5 edited

Legend:

Unmodified
Added
Removed
  • arch/ia64/include/context.h

    re0cdb7b6 ra016b63  
    5050#define context_set(c, _pc, stack, size)                                                \
    5151        (c)->pc = (__address) _pc;                                                      \
    52         (c)->bsp = ((__address) stack) + (ALIGN(sizeof(the_t), STACK_ALIGNMENT));       \
    53         (c)->sp = ((__address) stack) + (size) - SP_DELTA;
     52        (c)->bsp = ((__address) stack) + ALIGN(sizeof(the_t), STACK_ALIGNMENT);         \
     53        (c)->sp = ((__address) stack) + ALIGN((size) - SP_DELTA, STACK_ALIGNMENT);
    5454
    5555/*
  • arch/mips32/include/mm/page.h

    re0cdb7b6 ra016b63  
    6363#define SET_PTL0_ADDRESS_ARCH(ptl0)             (PTL0 = (pte_t *)(ptl0))
    6464
    65 #define GET_PTL1_ADDRESS_ARCH(ptl0, i)          (((pte_t *)(ptl0))[(i)].pfn<<12)
     65#define GET_PTL1_ADDRESS_ARCH(ptl0, i)          (((pte_t *)(ptl0))[(i)].lo.pfn<<12)
    6666#define GET_PTL2_ADDRESS_ARCH(ptl1, i)          (ptl1)
    6767#define GET_PTL3_ADDRESS_ARCH(ptl2, i)          (ptl2)
    68 #define GET_FRAME_ADDRESS_ARCH(ptl3, i)         (((pte_t *)(ptl3))[(i)].pfn<<12)
     68#define GET_FRAME_ADDRESS_ARCH(ptl3, i)         (((pte_t *)(ptl3))[(i)].lo.pfn<<12)
    6969
    70 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)       (((pte_t *)(ptl0))[(i)].pfn = (a)>>12)
     70#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)       (((pte_t *)(ptl0))[(i)].lo.pfn = (a)>>12)
    7171#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
    7272#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
    73 #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)      (((pte_t *)(ptl3))[(i)].pfn = (a)>>12)
     73#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)      (((pte_t *)(ptl3))[(i)].lo.pfn = (a)>>12)
    7474
    7575#define GET_PTL1_FLAGS_ARCH(ptl0, i)            get_pt_flags((pte_t *)(ptl0), (index_t)(i))
     
    9595       
    9696        return (
    97                 ((p->c>PAGE_UNCACHED)<<PAGE_CACHEABLE_SHIFT) |
    98                 ((!p->v)<<PAGE_PRESENT_SHIFT) |
     97                ((p->lo.c>PAGE_UNCACHED)<<PAGE_CACHEABLE_SHIFT) |
     98                ((!p->lo.v)<<PAGE_PRESENT_SHIFT) |
    9999                (1<<PAGE_USER_SHIFT) |
    100100                (1<<PAGE_READ_SHIFT) |
     
    109109        pte_t *p = &pt[i];
    110110       
    111         p->c = (flags & PAGE_CACHEABLE) != 0 ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
    112         p->v = !(flags & PAGE_NOT_PRESENT);
     111        p->lo.c = (flags & PAGE_CACHEABLE) != 0 ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
     112        p->lo.v = !(flags & PAGE_NOT_PRESENT);
    113113        p->w = (flags & PAGE_WRITE) != 0;
    114114}
  • arch/mips32/include/mm/tlb.h

    re0cdb7b6 ra016b63  
    3131
    3232#include <arch/exception.h>
     33#include <typedefs.h>
    3334
    3435#define TLB_SIZE        48
     
    4142#define PAGE_UNCACHED                   2
    4243#define PAGE_CACHEABLE_EXC_WRITE        5
     44
     45typedef union entry_lo entry_lo_t;
     46typedef union entry_hi entry_hi_t;
     47typedef union page_mask page_mask_t;
     48typedef union index tlb_index_t;
    4349
    4450union entry_lo {
     
    5460};
    5561
    56 struct pte {
    57         unsigned g : 1;         /* global bit */
    58         unsigned v : 1;         /* valid bit */
    59         unsigned d : 1;         /* dirty/write-protect bit */
    60         unsigned c : 3;         /* cache coherency attribute */
    61         unsigned pfn : 24;      /* frame number */
    62         unsigned w : 1;         /* writable */
    63         unsigned a : 1;         /* accessed */
    64 } __attribute__ ((packed));
     62union pte {
     63        entry_lo_t lo;
     64        struct {
     65                unsigned : 30;
     66                unsigned w : 1;         /* writable */
     67                unsigned a : 1;         /* accessed */
     68        } __attribute__ ((packed));
     69};
    6570
    6671union entry_hi {
     
    9095        __u32 value;
    9196};
    92 
    93 typedef union entry_lo entry_lo_t;
    94 typedef union entry_hi entry_hi_t;
    95 typedef union page_mask page_mask_t;
    96 typedef union index tlb_index_t;
    9797
    9898/** Probe TLB for Matching Entry
  • arch/mips32/include/types.h

    re0cdb7b6 ra016b63  
    5050typedef __u32 __native;
    5151
    52 typedef struct pte pte_t;
     52typedef union pte pte_t;
    5353
    5454#endif
  • arch/mips32/src/mm/tlb.c

    re0cdb7b6 ra016b63  
    105105
    106106        prepare_entry_hi(&hi, VM->asid, badvaddr);
    107         prepare_entry_lo(&lo, pte->g, pte->v, pte->d, pte->c, pte->pfn);
     107        prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->lo.d, pte->lo.c, pte->lo.pfn);
    108108
    109109        /*
     
    178178        pte->a = 1;
    179179
    180         prepare_entry_lo(&lo, pte->g, pte->v, pte->d, pte->c, pte->pfn);
     180        prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->lo.d, pte->lo.c, pte->lo.pfn);
    181181
    182182        /*
     
    251251         */
    252252        pte->a = 1;
    253         pte->d = 1;
    254 
    255         prepare_entry_lo(&lo, pte->g, pte->v, pte->w, pte->c, pte->pfn);
     253        pte->lo.d = 1;
     254
     255        prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->w, pte->lo.c, pte->lo.pfn);
    256256
    257257        /*
     
    376376         * Handler cannot succeed if the mapping is marked as invalid.
    377377         */
    378         if (!pte->v) {
     378        if (!pte->lo.v) {
    379379                printf("Invalid mapping.\n");
    380380                return NULL;
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