Changes in kernel/genarch/src/mm/page_pt.c [de73242:a2789d2] in mainline
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kernel/genarch/src/mm/page_pt.c
rde73242 ra2789d2 43 43 #include <arch/mm/page.h> 44 44 #include <arch/mm/as.h> 45 #include <arch/barrier.h>46 45 #include <typedefs.h> 47 46 #include <arch/asm.h> … … 49 48 #include <align.h> 50 49 #include <macros.h> 51 #include <bitops.h>52 50 53 51 static void pt_mapping_insert(as_t *, uintptr_t, uintptr_t, unsigned int); … … 87 85 SET_PTL1_ADDRESS(ptl0, PTL0_INDEX(page), KA2PA(newpt)); 88 86 SET_PTL1_FLAGS(ptl0, PTL0_INDEX(page), 89 PAGE_ NOT_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |87 PAGE_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE | 90 88 PAGE_WRITE); 91 /*92 * Make sure that a concurrent hardware page table walk or93 * pt_mapping_find() will see the new PTL1 only after it is94 * fully initialized.95 */96 write_barrier();97 SET_PTL1_PRESENT(ptl0, PTL0_INDEX(page));98 89 } 99 90 … … 106 97 SET_PTL2_ADDRESS(ptl1, PTL1_INDEX(page), KA2PA(newpt)); 107 98 SET_PTL2_FLAGS(ptl1, PTL1_INDEX(page), 108 PAGE_ NOT_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |99 PAGE_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE | 109 100 PAGE_WRITE); 110 /*111 * Make the new PTL2 visible only after it is fully initialized.112 */113 write_barrier();114 SET_PTL2_PRESENT(ptl1, PTL1_INDEX(page));115 101 } 116 102 … … 123 109 SET_PTL3_ADDRESS(ptl2, PTL2_INDEX(page), KA2PA(newpt)); 124 110 SET_PTL3_FLAGS(ptl2, PTL2_INDEX(page), 125 PAGE_ NOT_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |111 PAGE_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE | 126 112 PAGE_WRITE); 127 /*128 * Make the new PTL3 visible only after it is fully initialized.129 */130 write_barrier();131 SET_PTL3_PRESENT(ptl2, PTL2_INDEX(page));132 113 } 133 114 … … 135 116 136 117 SET_FRAME_ADDRESS(ptl3, PTL3_INDEX(page), frame); 137 SET_FRAME_FLAGS(ptl3, PTL3_INDEX(page), flags | PAGE_NOT_PRESENT); 138 /* 139 * Make the new mapping visible only after it is fully initialized. 140 */ 141 write_barrier(); 142 SET_FRAME_PRESENT(ptl3, PTL3_INDEX(page)); 118 SET_FRAME_FLAGS(ptl3, PTL3_INDEX(page), flags); 143 119 } 144 120 … … 302 278 if (GET_PTL1_FLAGS(ptl0, PTL0_INDEX(page)) & PAGE_NOT_PRESENT) 303 279 return NULL; 304 305 read_barrier();306 280 307 281 pte_t *ptl1 = (pte_t *) PA2KA(GET_PTL1_ADDRESS(ptl0, PTL0_INDEX(page))); 308 282 if (GET_PTL2_FLAGS(ptl1, PTL1_INDEX(page)) & PAGE_NOT_PRESENT) 309 283 return NULL; 310 311 #if (PTL1_ENTRIES != 0)312 /*313 * Always read ptl2 only after we are sure it is present.314 */315 read_barrier();316 #endif317 284 318 285 pte_t *ptl2 = (pte_t *) PA2KA(GET_PTL2_ADDRESS(ptl1, PTL1_INDEX(page))); 319 286 if (GET_PTL3_FLAGS(ptl2, PTL2_INDEX(page)) & PAGE_NOT_PRESENT) 320 287 return NULL; 321 322 #if (PTL2_ENTRIES != 0)323 /*324 * Always read ptl3 only after we are sure it is present.325 */326 read_barrier();327 #endif328 288 329 289 pte_t *ptl3 = (pte_t *) PA2KA(GET_PTL3_ADDRESS(ptl2, PTL2_INDEX(page))); 330 290 331 291 return &ptl3[PTL3_INDEX(page)]; 332 }333 334 /** Return the size of the region mapped by a single PTL0 entry.335 *336 * @return Size of the region mapped by a single PTL0 entry.337 */338 static uintptr_t ptl0_step_get(void)339 {340 size_t va_bits;341 342 va_bits = fnzb(PTL0_ENTRIES) + fnzb(PTL1_ENTRIES) + fnzb(PTL2_ENTRIES) +343 fnzb(PTL3_ENTRIES) + PAGE_WIDTH;344 345 return 1UL << (va_bits - fnzb(PTL0_ENTRIES));346 292 } 347 293 … … 363 309 { 364 310 uintptr_t ptl0 = PA2KA((uintptr_t) AS_KERNEL->genarch.page_table); 365 uintptr_t ptl0 _step = ptl0_step_get();311 uintptr_t ptl0step = (((uintptr_t) -1) / PTL0_ENTRIES) + 1; 366 312 size_t order; 367 313 uintptr_t addr; … … 375 321 #endif 376 322 323 ASSERT(ispwr2(ptl0step)); 377 324 ASSERT(size > 0); 378 325 379 for (addr = ALIGN_DOWN(base, ptl0 _step); addr - 1 < base + size - 1;380 addr += ptl0 _step) {326 for (addr = ALIGN_DOWN(base, ptl0step); addr - 1 < base + size - 1; 327 addr += ptl0step) { 381 328 uintptr_t l1; 382 329 … … 385 332 SET_PTL1_ADDRESS(ptl0, PTL0_INDEX(addr), KA2PA(l1)); 386 333 SET_PTL1_FLAGS(ptl0, PTL0_INDEX(addr), 387 PAGE_PRESENT | PAGE_USER | PAGE_ CACHEABLE |388 PAGE_ EXEC | PAGE_WRITE | PAGE_READ);334 PAGE_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE | 335 PAGE_WRITE); 389 336 } 390 337 }
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