Changes in boot/arch/mips32/src/asm.S [7cedc46a:a2da43c] in mainline
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boot/arch/mips32/src/asm.S
r7cedc46a ra2da43c 41 41 42 42 start: 43 /* 44 * Setup the CP0 configuration 45 * - Disable 64-bit kernel addressing mode 46 * - DIsable 64-bit supervisor adressing mode 47 * - Disable 64-bit user addressing mode 48 */ 49 mfc0 $a0, $status 50 la $a1, 0xffffff1f 51 and $a0, $a1, $a0 52 mtc0 $a0, $status 53 54 /* 55 * Setup CPU map (on msim this code 56 * is executed in parallel on all CPUs, 57 * but it not an issue). 58 */ 43 /* Setup CPU map (on msim this code 44 is executed in parallel on all CPUs, 45 but it not an issue) */ 59 46 la $a0, PA2KA(CPUMAP_OFFSET) 60 47 … … 107 94 lw $k1, ($k0) 108 95 109 /* 110 * If we are not running on BSP 111 * then end in an infinite loop. 112 */ 96 /* If we are not running on BSP 97 then end in an infinite loop */ 113 98 beq $k1, $zero, bsp 114 99 nop … … 142 127 143 128 jump_to_kernel: 144 /* 145 * TODO: 146 * 147 * Make sure that the I-cache, D-cache and memory are mutually 148 * coherent before passing control to the copied code. 149 */ 129 # 130 # TODO: 131 # Make sure that the I-cache, D-cache and memory are mutually coherent 132 # before passing control to the copied code. 133 # 150 134 j $a0 151 135 nop
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