Changeset a35b458 in mainline for uspace/drv/block/ahci/ahci.c
- Timestamp:
- 2018-03-02T20:10:49Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- f1380b7
- Parents:
- 3061bc1
- git-author:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-02-28 17:38:31)
- git-committer:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-03-02 20:10:49)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/block/ahci/ahci.c
r3061bc1 ra35b458 229 229 { 230 230 sata_dev_t *sata = fun_sata_dev(fun); 231 231 232 232 uintptr_t phys; 233 233 void *ibuf = AS_AREA_ANY; … … 238 238 return rc; 239 239 } 240 240 241 241 memset(buf, 0, sata->block_size); 242 242 243 243 fibril_mutex_lock(&sata->lock); 244 244 245 245 for (size_t cur = 0; cur < count; cur++) { 246 246 rc = ahci_rb_fpdma(sata, phys, blocknum + cur); 247 247 if (rc != EOK) 248 248 break; 249 249 250 250 memcpy((void *) (((uint8_t *) buf) + (sata->block_size * cur)), 251 251 ibuf, sata->block_size); 252 252 } 253 253 254 254 fibril_mutex_unlock(&sata->lock); 255 255 dmamem_unmap_anonymous(ibuf); 256 256 257 257 return rc; 258 258 } … … 272 272 { 273 273 sata_dev_t *sata = fun_sata_dev(fun); 274 274 275 275 uintptr_t phys; 276 276 void *ibuf = AS_AREA_ANY; … … 281 281 return rc; 282 282 } 283 283 284 284 fibril_mutex_lock(&sata->lock); 285 285 286 286 for (size_t cur = 0; cur < count; cur++) { 287 287 memcpy(ibuf, (void *) (((uint8_t *) buf) + (sata->block_size * cur)), … … 291 291 break; 292 292 } 293 293 294 294 fibril_mutex_unlock(&sata->lock); 295 295 dmamem_unmap_anonymous(ibuf); 296 296 297 297 return rc; 298 298 } … … 312 312 { 313 313 fibril_mutex_lock(&sata->event_lock); 314 314 315 315 sata->event_pxis = 0; 316 316 while (sata->event_pxis == 0) 317 317 fibril_condvar_wait(&sata->event_condvar, &sata->event_lock); 318 318 319 319 ahci_port_is_t pxis = sata->event_pxis; 320 320 321 321 if (ahci_port_is_permanent_error(pxis)) 322 322 sata->is_invalid_device = true; 323 323 324 324 fibril_mutex_unlock(&sata->event_lock); 325 325 326 326 return pxis; 327 327 } … … 337 337 volatile sata_std_command_frame_t *cmd = 338 338 (sata_std_command_frame_t *) sata->cmd_table; 339 339 340 340 cmd->fis_type = SATA_CMD_FIS_TYPE; 341 341 cmd->c = SATA_CMD_FIS_COMMAND_INDICATOR; … … 350 350 cmd->control = 0; 351 351 cmd->reserved2 = 0; 352 352 353 353 volatile ahci_cmd_prdt_t *prdt = 354 354 (ahci_cmd_prdt_t *) (&sata->cmd_table[0x20]); 355 355 356 356 prdt->data_address_low = LO(phys); 357 357 prdt->data_address_upper = HI(phys); … … 360 360 prdt->reserved2 = 0; 361 361 prdt->ioc = 0; 362 362 363 363 sata->cmd_header->prdtl = 1; 364 364 sata->cmd_header->flags = … … 366 366 AHCI_CMDHDR_FLAGS_2DWCMD; 367 367 sata->cmd_header->bytesprocessed = 0; 368 368 369 369 /* Run command. */ 370 370 sata->port->pxsact |= 1; … … 382 382 volatile sata_std_command_frame_t *cmd = 383 383 (sata_std_command_frame_t *) sata->cmd_table; 384 384 385 385 cmd->fis_type = SATA_CMD_FIS_TYPE; 386 386 cmd->c = SATA_CMD_FIS_COMMAND_INDICATOR; … … 395 395 cmd->control = 0; 396 396 cmd->reserved2 = 0; 397 397 398 398 volatile ahci_cmd_prdt_t *prdt = 399 399 (ahci_cmd_prdt_t *) (&sata->cmd_table[0x20]); 400 400 401 401 prdt->data_address_low = LO(phys); 402 402 prdt->data_address_upper = HI(phys); … … 405 405 prdt->reserved2 = 0; 406 406 prdt->ioc = 0; 407 407 408 408 sata->cmd_header->prdtl = 1; 409 409 sata->cmd_header->flags = … … 411 411 AHCI_CMDHDR_FLAGS_2DWCMD; 412 412 sata->cmd_header->bytesprocessed = 0; 413 413 414 414 /* Run command. */ 415 415 sata->port->pxsact |= 1; … … 431 431 return EINTR; 432 432 } 433 433 434 434 uintptr_t phys; 435 435 sata_identify_data_t *idata = AS_AREA_ANY; … … 441 441 return rc; 442 442 } 443 443 444 444 memset(idata, 0, SATA_IDENTIFY_DEVICE_BUFFER_LENGTH); 445 445 446 446 fibril_mutex_lock(&sata->lock); 447 447 448 448 ahci_identify_device_cmd(sata, phys); 449 449 ahci_port_is_t pxis = ahci_wait_event(sata); 450 450 451 451 if (sata->is_invalid_device) { 452 452 ddf_msg(LVL_ERROR, … … 454 454 goto error; 455 455 } 456 456 457 457 if (ahci_port_is_tfes(pxis)) { 458 458 ahci_identify_packet_device_cmd(sata, phys); 459 459 pxis = ahci_wait_event(sata); 460 460 461 461 if ((sata->is_invalid_device) || (ahci_port_is_error(pxis))) { 462 462 ddf_msg(LVL_ERROR, … … 464 464 goto error; 465 465 } 466 466 467 467 sata->is_packet_device = true; 468 468 } 469 469 470 470 ahci_get_model_name(idata->model_name, sata->model); 471 471 472 472 /* 473 473 * Due to QEMU limitation (as of 2012-06-22), … … 478 478 goto error; 479 479 } 480 480 481 481 uint16_t logsec = idata->physical_logic_sector_size; 482 482 if ((logsec & 0xc000) == 0x4000) { … … 489 489 goto error; 490 490 } 491 491 492 492 if ((logsec & 0x0200) && ((logsec & 0x000f) != 0)) { 493 493 /* Physical sectors per logical sector is greather than 1 */ … … 498 498 } 499 499 } 500 500 501 501 if (sata->is_packet_device) { 502 502 /* … … 509 509 } else { 510 510 sata->block_size = SATA_DEFAULT_SECTOR_SIZE; 511 511 512 512 if ((idata->caps & sata_rd_cap_lba) == 0) { 513 513 ddf_msg(LVL_ERROR, "%s: LBA for NCQ must be supported", … … 525 525 } 526 526 } 527 527 528 528 uint8_t udma_mask = idata->udma & 0x007f; 529 529 sata->highest_udma_mode = (uint8_t) -1; … … 539 539 } 540 540 } 541 541 542 542 fibril_mutex_unlock(&sata->lock); 543 543 dmamem_unmap_anonymous(idata); 544 544 545 545 return EOK; 546 546 547 547 error: 548 548 fibril_mutex_unlock(&sata->lock); 549 549 dmamem_unmap_anonymous(idata); 550 550 551 551 return EINTR; 552 552 } … … 563 563 volatile sata_std_command_frame_t *cmd = 564 564 (sata_std_command_frame_t *) sata->cmd_table; 565 565 566 566 cmd->fis_type = SATA_CMD_FIS_TYPE; 567 567 cmd->c = SATA_CMD_FIS_COMMAND_INDICATOR; … … 576 576 cmd->control = 0; 577 577 cmd->reserved2 = 0; 578 578 579 579 volatile ahci_cmd_prdt_t *prdt = 580 580 (ahci_cmd_prdt_t *) (&sata->cmd_table[0x20]); 581 581 582 582 prdt->data_address_low = LO(phys); 583 583 prdt->data_address_upper = HI(phys); … … 586 586 prdt->reserved2 = 0; 587 587 prdt->ioc = 0; 588 588 589 589 sata->cmd_header->prdtl = 1; 590 590 sata->cmd_header->flags = … … 592 592 AHCI_CMDHDR_FLAGS_2DWCMD; 593 593 sata->cmd_header->bytesprocessed = 0; 594 594 595 595 /* Run command. */ 596 596 sata->port->pxsact |= 1; … … 613 613 return EINTR; 614 614 } 615 615 616 616 if (sata->highest_udma_mode == (uint8_t) -1) { 617 617 ddf_msg(LVL_ERROR, … … 619 619 return EINTR; 620 620 } 621 621 622 622 if (sata->highest_udma_mode > 6) { 623 623 ddf_msg(LVL_ERROR, … … 625 625 return EINTR; 626 626 } 627 627 628 628 uintptr_t phys; 629 629 sata_identify_data_t *idata = AS_AREA_ANY; … … 635 635 return rc; 636 636 } 637 637 638 638 memset(idata, 0, SATA_SET_FEATURE_BUFFER_LENGTH); 639 639 640 640 fibril_mutex_lock(&sata->lock); 641 641 642 642 uint8_t mode = 0x40 | (sata->highest_udma_mode & 0x07); 643 643 ahci_set_mode_cmd(sata, phys, mode); 644 644 ahci_port_is_t pxis = ahci_wait_event(sata); 645 645 646 646 if (sata->is_invalid_device) { 647 647 ddf_msg(LVL_ERROR, … … 650 650 goto error; 651 651 } 652 652 653 653 if (ahci_port_is_error(pxis)) { 654 654 ddf_msg(LVL_ERROR, … … 656 656 goto error; 657 657 } 658 658 659 659 fibril_mutex_unlock(&sata->lock); 660 660 dmamem_unmap_anonymous(idata); 661 661 662 662 return EOK; 663 663 664 664 error: 665 665 fibril_mutex_unlock(&sata->lock); 666 666 dmamem_unmap_anonymous(idata); 667 667 668 668 return EINTR; 669 669 } … … 681 681 volatile sata_ncq_command_frame_t *cmd = 682 682 (sata_ncq_command_frame_t *) sata->cmd_table; 683 683 684 684 cmd->fis_type = SATA_CMD_FIS_TYPE; 685 685 cmd->c = SATA_CMD_FIS_COMMAND_INDICATOR; … … 687 687 cmd->tag = 0; 688 688 cmd->control = 0; 689 689 690 690 cmd->reserved1 = 0; 691 691 cmd->reserved2 = 0; … … 694 694 cmd->reserved5 = 0; 695 695 cmd->reserved6 = 0; 696 696 697 697 cmd->sector_count_low = 1; 698 698 cmd->sector_count_high = 0; 699 699 700 700 cmd->lba0 = blocknum & 0xff; 701 701 cmd->lba1 = (blocknum >> 8) & 0xff; … … 704 704 cmd->lba4 = (blocknum >> 32) & 0xff; 705 705 cmd->lba5 = (blocknum >> 40) & 0xff; 706 706 707 707 volatile ahci_cmd_prdt_t *prdt = 708 708 (ahci_cmd_prdt_t *) (&sata->cmd_table[0x20]); 709 709 710 710 prdt->data_address_low = LO(phys); 711 711 prdt->data_address_upper = HI(phys); … … 714 714 prdt->reserved2 = 0; 715 715 prdt->ioc = 0; 716 716 717 717 sata->cmd_header->prdtl = 1; 718 718 sata->cmd_header->flags = … … 720 720 AHCI_CMDHDR_FLAGS_5DWCMD; 721 721 sata->cmd_header->bytesprocessed = 0; 722 722 723 723 sata->port->pxsact |= 1; 724 724 sata->port->pxci |= 1; … … 741 741 return EINTR; 742 742 } 743 743 744 744 ahci_rb_fpdma_cmd(sata, phys, blocknum); 745 745 ahci_port_is_t pxis = ahci_wait_event(sata); 746 746 747 747 if ((sata->is_invalid_device) || (ahci_port_is_error(pxis))) { 748 748 ddf_msg(LVL_ERROR, … … 750 750 return EINTR; 751 751 } 752 752 753 753 return EOK; 754 754 } … … 768 768 volatile sata_ncq_command_frame_t *cmd = 769 769 (sata_ncq_command_frame_t *) sata->cmd_table; 770 770 771 771 cmd->fis_type = SATA_CMD_FIS_TYPE; 772 772 cmd->c = SATA_CMD_FIS_COMMAND_INDICATOR; … … 774 774 cmd->tag = 0; 775 775 cmd->control = 0; 776 776 777 777 cmd->reserved1 = 0; 778 778 cmd->reserved2 = 0; … … 781 781 cmd->reserved5 = 0; 782 782 cmd->reserved6 = 0; 783 783 784 784 cmd->sector_count_low = 1; 785 785 cmd->sector_count_high = 0; 786 786 787 787 cmd->lba0 = blocknum & 0xff; 788 788 cmd->lba1 = (blocknum >> 8) & 0xff; … … 791 791 cmd->lba4 = (blocknum >> 32) & 0xff; 792 792 cmd->lba5 = (blocknum >> 40) & 0xff; 793 793 794 794 volatile ahci_cmd_prdt_t *prdt = 795 795 (ahci_cmd_prdt_t *) (&sata->cmd_table[0x20]); 796 796 797 797 prdt->data_address_low = LO(phys); 798 798 prdt->data_address_upper = HI(phys); … … 801 801 prdt->reserved2 = 0; 802 802 prdt->ioc = 0; 803 803 804 804 sata->cmd_header->prdtl = 1; 805 805 sata->cmd_header->flags = … … 808 808 AHCI_CMDHDR_FLAGS_5DWCMD; 809 809 sata->cmd_header->bytesprocessed = 0; 810 810 811 811 sata->port->pxsact |= 1; 812 812 sata->port->pxci |= 1; … … 829 829 return EINTR; 830 830 } 831 831 832 832 ahci_wb_fpdma_cmd(sata, phys, blocknum); 833 833 ahci_port_is_t pxis = ahci_wait_event(sata); 834 834 835 835 if ((sata->is_invalid_device) || (ahci_port_is_error(pxis))) { 836 836 ddf_msg(LVL_ERROR, … … 838 838 return EINTR; 839 839 } 840 840 841 841 return EOK; 842 842 } … … 899 899 unsigned int port = IPC_GET_ARG1(*icall); 900 900 ahci_port_is_t pxis = IPC_GET_ARG2(*icall); 901 901 902 902 if (port >= AHCI_MAX_PORTS) 903 903 return; 904 904 905 905 sata_dev_t *sata = (sata_dev_t *) ahci->sata_devs[port]; 906 906 if (sata == NULL) 907 907 return; 908 908 909 909 /* Evaluate port event */ 910 910 if ((ahci_port_is_end_of_operation(pxis)) || 911 911 (ahci_port_is_error(pxis))) { 912 912 fibril_mutex_lock(&sata->event_lock); 913 913 914 914 sata->event_pxis = pxis; 915 915 fibril_condvar_signal(&sata->event_condvar); 916 916 917 917 fibril_mutex_unlock(&sata->event_lock); 918 918 } … … 938 938 void *virt_table = AS_AREA_ANY; 939 939 ddf_fun_t *fun; 940 940 941 941 fun = ddf_fun_create(ahci->dev, fun_exposed, NULL); 942 942 943 943 sata_dev_t *sata = ddf_fun_data_alloc(fun, sizeof(sata_dev_t)); 944 944 if (sata == NULL) 945 945 return NULL; 946 946 947 947 sata->fun = fun; 948 948 sata->port = port; 949 949 950 950 /* Allocate and init retfis structure. */ 951 951 errno_t rc = dmamem_map_anonymous(size, DMAMEM_4GiB, … … 953 953 if (rc != EOK) 954 954 goto error_retfis; 955 955 956 956 memset(virt_fb, 0, size); 957 957 sata->port->pxfbu = HI(phys); 958 958 sata->port->pxfb = LO(phys); 959 959 960 960 /* Allocate and init command header structure. */ 961 961 rc = dmamem_map_anonymous(size, DMAMEM_4GiB, … … 963 963 if (rc != EOK) 964 964 goto error_cmd; 965 965 966 966 memset(virt_cmd, 0, size); 967 967 sata->port->pxclbu = HI(phys); 968 968 sata->port->pxclb = LO(phys); 969 969 sata->cmd_header = (ahci_cmdhdr_t *) virt_cmd; 970 970 971 971 /* Allocate and init command table structure. */ 972 972 rc = dmamem_map_anonymous(size, DMAMEM_4GiB, … … 974 974 if (rc != EOK) 975 975 goto error_table; 976 976 977 977 memset(virt_table, 0, size); 978 978 sata->cmd_header->cmdtableu = HI(phys); 979 979 sata->cmd_header->cmdtable = LO(phys); 980 980 sata->cmd_table = (uint32_t*) virt_table; 981 981 982 982 return sata; 983 983 984 984 error_table: 985 985 dmamem_unmap(virt_cmd, size); … … 999 999 { 1000 1000 ahci_port_cmd_t pxcmd; 1001 1001 1002 1002 pxcmd.u32 = sata->port->pxcmd; 1003 1003 1004 1004 /* Frame receiver disabled. */ 1005 1005 pxcmd.fre = 0; 1006 1006 1007 1007 /* Disable process the command list. */ 1008 1008 pxcmd.st = 0; 1009 1009 1010 1010 sata->port->pxcmd = pxcmd.u32; 1011 1011 1012 1012 /* Clear interrupt status. */ 1013 1013 sata->port->pxis = 0xffffffff; 1014 1014 1015 1015 /* Clear error status. */ 1016 1016 sata->port->pxserr = 0xffffffff; 1017 1017 1018 1018 /* Enable all interrupts. */ 1019 1019 sata->port->pxie = 0xffffffff; 1020 1020 1021 1021 /* Frame receiver enabled. */ 1022 1022 pxcmd.fre = 1; 1023 1023 1024 1024 /* Enable process the command list. */ 1025 1025 pxcmd.st = 1; 1026 1026 1027 1027 sata->port->pxcmd = pxcmd.u32; 1028 1028 } … … 1043 1043 ddf_fun_t *fun = NULL; 1044 1044 errno_t rc; 1045 1045 1046 1046 sata_dev_t *sata = ahci_sata_allocate(ahci, port); 1047 1047 if (sata == NULL) 1048 1048 return EINTR; 1049 1049 1050 1050 /* Set pointers between SATA and AHCI structures. */ 1051 1051 sata->ahci = ahci; 1052 1052 sata->port_num = port_num; 1053 1053 ahci->sata_devs[port_num] = sata; 1054 1054 1055 1055 /* Initialize synchronization structures */ 1056 1056 fibril_mutex_initialize(&sata->lock); 1057 1057 fibril_mutex_initialize(&sata->event_lock); 1058 1058 fibril_condvar_initialize(&sata->event_condvar); 1059 1059 1060 1060 ahci_sata_hw_start(sata); 1061 1061 1062 1062 /* Identify device. */ 1063 1063 if (ahci_identify_device(sata) != EOK) 1064 1064 goto error; 1065 1065 1066 1066 /* Set required UDMA mode */ 1067 1067 if (ahci_set_highest_ultra_dma_mode(sata) != EOK) 1068 1068 goto error; 1069 1069 1070 1070 /* Add device to the system */ 1071 1071 char sata_dev_name[16]; 1072 1072 snprintf(sata_dev_name, 16, "ahci_%u", sata_devices_count); 1073 1073 1074 1074 fibril_mutex_lock(&sata_devices_count_lock); 1075 1075 sata_devices_count++; 1076 1076 fibril_mutex_unlock(&sata_devices_count_lock); 1077 1077 1078 1078 rc= ddf_fun_set_name(sata->fun, sata_dev_name); 1079 1079 if (rc != EOK) { … … 1081 1081 goto error; 1082 1082 } 1083 1083 1084 1084 ddf_fun_set_ops(fun, &ahci_ops); 1085 1085 1086 1086 rc = ddf_fun_bind(fun); 1087 1087 if (rc != EOK) { … … 1089 1089 goto error; 1090 1090 } 1091 1091 1092 1092 return EOK; 1093 1093 1094 1094 error: 1095 1095 sata->is_invalid_device = true; 1096 1096 if (fun != NULL) 1097 1097 ddf_fun_destroy(fun); 1098 1098 1099 1099 return EINTR; 1100 1100 } … … 1112 1112 if (!(ahci->memregs->ghc.pi & (1 << port_num))) 1113 1113 continue; 1114 1114 1115 1115 volatile ahci_port_t *port = ahci->memregs->ports + port_num; 1116 1116 1117 1117 /* Active devices only */ 1118 1118 ahci_port_ssts_t pxssts; … … 1120 1120 if (pxssts.det != AHCI_PORT_SSTS_DET_ACTIVE) 1121 1121 continue; 1122 1122 1123 1123 ahci_sata_create(ahci, dev, port, port_num); 1124 1124 } … … 1137 1137 if (!ahci) 1138 1138 return NULL; 1139 1139 1140 1140 /* Connect to parent device */ 1141 1141 ahci->parent_sess = ddf_dev_parent_sess_get(dev); 1142 1142 if (ahci->parent_sess == NULL) 1143 1143 return NULL; 1144 1144 1145 1145 ahci->dev = dev; 1146 1146 1147 1147 hw_res_list_parsed_t hw_res_parsed; 1148 1148 hw_res_list_parsed_init(&hw_res_parsed); 1149 1149 if (hw_res_get_list_parsed(ahci->parent_sess, &hw_res_parsed, 0) != EOK) 1150 1150 goto error_get_res_parsed; 1151 1151 1152 1152 /* Map AHCI registers. */ 1153 1153 ahci->memregs = AS_AREA_ANY; 1154 1154 1155 1155 physmem_map(RNGABS(hw_res_parsed.mem_ranges.ranges[0]), 1156 1156 AHCI_MEMREGS_PAGES_COUNT, AS_AREA_READ | AS_AREA_WRITE, … … 1158 1158 if (ahci->memregs == NULL) 1159 1159 goto error_map_registers; 1160 1160 1161 1161 /* Register interrupt handler */ 1162 1162 ahci_ranges[0].base = RNGABS(hw_res_parsed.mem_ranges.ranges[0]); 1163 1163 ahci_ranges[0].size = sizeof(ahci_memregs_t); 1164 1164 1165 1165 for (unsigned int port = 0; port < AHCI_MAX_PORTS; port++) { 1166 1166 size_t base = port * 7; 1167 1167 1168 1168 ahci_cmds[base].addr = 1169 1169 ((uint32_t *) RNGABSPTR(hw_res_parsed.mem_ranges.ranges[0])) + … … 1171 1171 AHCI_PORT_IS_REGISTER_OFFSET; 1172 1172 ahci_cmds[base + 2].addr = ahci_cmds[base].addr; 1173 1173 1174 1174 ahci_cmds[base + 3].addr = 1175 1175 ((uint32_t *) RNGABSPTR(hw_res_parsed.mem_ranges.ranges[0])) + … … 1177 1177 ahci_cmds[base + 4].addr = ahci_cmds[base + 3].addr; 1178 1178 } 1179 1179 1180 1180 irq_code_t ct; 1181 1181 ct.cmdcount = sizeof(ahci_cmds) / sizeof(irq_cmd_t); … … 1183 1183 ct.rangecount = sizeof(ahci_ranges) / sizeof(irq_pio_range_t); 1184 1184 ct.ranges = ahci_ranges; 1185 1185 1186 1186 int irq_cap; 1187 1187 errno_t rc = register_interrupt_handler(dev, … … 1191 1191 goto error_register_interrupt_handler; 1192 1192 } 1193 1193 1194 1194 rc = hw_res_enable_interrupt(ahci->parent_sess, 1195 1195 hw_res_parsed.irqs.irqs[0]); … … 1198 1198 goto error_enable_interrupt; 1199 1199 } 1200 1200 1201 1201 hw_res_list_parsed_clean(&hw_res_parsed); 1202 1202 return ahci; 1203 1203 1204 1204 error_enable_interrupt: 1205 1205 unregister_interrupt_handler(dev, irq_cap); 1206 1206 1207 1207 error_register_interrupt_handler: 1208 1208 // FIXME: unmap physical memory 1209 1209 1210 1210 error_map_registers: 1211 1211 hw_res_list_parsed_clean(&hw_res_parsed); 1212 1212 1213 1213 error_get_res_parsed: 1214 1214 free(ahci); … … 1225 1225 /* Disable command completion coalescing feature */ 1226 1226 ahci_ghc_ccc_ctl_t ccc; 1227 1227 1228 1228 ccc.u32 = ahci->memregs->ghc.ccc_ctl; 1229 1229 ccc.en = 0; 1230 1230 ahci->memregs->ghc.ccc_ctl = ccc.u32; 1231 1231 1232 1232 /* Set master latency timer. */ 1233 1233 pci_config_space_write_8(ahci->parent_sess, AHCI_PCI_MLT, 32); 1234 1234 1235 1235 /* Enable PCI interrupt and bus mastering */ 1236 1236 ahci_pcireg_cmd_t cmd; 1237 1237 1238 1238 pci_config_space_read_16(ahci->parent_sess, AHCI_PCI_CMD, &cmd.u16); 1239 1239 cmd.id = 0; 1240 1240 cmd.bme = 1; 1241 1241 pci_config_space_write_16(ahci->parent_sess, AHCI_PCI_CMD, cmd.u16); 1242 1242 1243 1243 /* Enable AHCI and interrupt. */ 1244 1244 ahci->memregs->ghc.ghc = AHCI_GHC_GHC_AE | AHCI_GHC_GHC_IE; … … 1260 1260 if (ahci == NULL) 1261 1261 goto error; 1262 1262 1263 1263 /* Start AHCI hardware. */ 1264 1264 ahci_ahci_hw_start(ahci); 1265 1265 1266 1266 /* Create device structures for sata devices attached to AHCI. */ 1267 1267 ahci_sata_devices_create(ahci, dev); 1268 1268 1269 1269 return EOK; 1270 1270 1271 1271 error: 1272 1272 return EINTR; … … 1290 1290 uint8_t model[40]; 1291 1291 memset(model, 0, 40); 1292 1292 1293 1293 for (unsigned int i = 0; i < 20; i++) { 1294 1294 uint16_t w = src[i]; … … 1296 1296 model[2 * i + 1] = w & 0x00ff; 1297 1297 } 1298 1298 1299 1299 uint32_t len = 40; 1300 1300 while ((len > 0) && (model[len - 1] == 0x20)) 1301 1301 len--; 1302 1302 1303 1303 size_t pos = 0; 1304 1304 for (unsigned int i = 0; i < len; i++) { … … 1306 1306 if (c >= 0x80) 1307 1307 c = '?'; 1308 1308 1309 1309 chr_encode(c, dst, &pos, 40); 1310 1310 } 1311 1311 1312 1312 dst[pos] = '\0'; 1313 1313 }
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