Changeset a35b458 in mainline for uspace/drv/nic/e1k/e1k.c
- Timestamp:
- 2018-03-02T20:10:49Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- f1380b7
- Parents:
- 3061bc1
- git-author:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-02-28 17:38:31)
- git-committer:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-03-02 20:10:49)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/nic/e1k/e1k.c
r3061bc1 ra35b458 122 122 /** Device configuration */ 123 123 e1000_info_t info; 124 124 125 125 /** Physical registers base address */ 126 126 void *reg_base_phys; 127 127 /** Virtual registers base address */ 128 128 void *reg_base_virt; 129 129 130 130 /** Physical tx ring address */ 131 131 uintptr_t tx_ring_phys; 132 132 /** Virtual tx ring address */ 133 133 void *tx_ring_virt; 134 134 135 135 /** Ring of TX frames, physical address */ 136 136 uintptr_t *tx_frame_phys; 137 137 /** Ring of TX frames, virtual address */ 138 138 void **tx_frame_virt; 139 139 140 140 /** Physical rx ring address */ 141 141 uintptr_t rx_ring_phys; 142 142 /** Virtual rx ring address */ 143 143 void *rx_ring_virt; 144 144 145 145 /** Ring of RX frames, physical address */ 146 146 uintptr_t *rx_frame_phys; 147 147 /** Ring of RX frames, virtual address */ 148 148 void **rx_frame_virt; 149 149 150 150 /** VLAN tag */ 151 151 uint16_t vlan_tag; 152 152 153 153 /** Add VLAN tag to frame */ 154 154 bool vlan_tag_add; 155 155 156 156 /** Used unicast Receive Address count */ 157 157 unsigned int unicast_ra_count; 158 158 159 159 /** Used milticast Receive addrress count */ 160 160 unsigned int multicast_ra_count; 161 161 162 162 /** The irq assigned */ 163 163 int irq; 164 164 165 165 /** Lock for CTRL register */ 166 166 fibril_mutex_t ctrl_lock; 167 167 168 168 /** Lock for receiver */ 169 169 fibril_mutex_t rx_lock; 170 170 171 171 /** Lock for transmitter */ 172 172 fibril_mutex_t tx_lock; 173 173 174 174 /** Lock for EEPROM access */ 175 175 fibril_mutex_t eeprom_lock; … … 292 292 assert(dev); 293 293 assert(info); 294 294 295 295 memset(info, 0, sizeof(nic_device_info_t)); 296 296 297 297 info->vendor_id = 0x8086; 298 298 str_cpy(info->vendor_name, NIC_VENDOR_MAX_LENGTH, … … 300 300 str_cpy(info->model_name, NIC_MODEL_MAX_LENGTH, 301 301 "Intel Pro"); 302 302 303 303 info->ethernet_support[ETH_10M] = ETH_10BASE_T; 304 304 info->ethernet_support[ETH_100M] = ETH_100BASE_TX; 305 305 info->ethernet_support[ETH_1000M] = ETH_1000BASE_T; 306 306 307 307 return EOK; 308 308 } … … 323 323 else 324 324 *state = NIC_CS_UNPLUGGED; 325 325 326 326 return EOK; 327 327 } … … 340 340 e1000_t *e1000 = DRIVER_DATA_FUN(fun); 341 341 uint32_t status = E1000_REG_READ(e1000, E1000_STATUS); 342 342 343 343 if (status & STATUS_FD) 344 344 *duplex = NIC_CM_FULL_DUPLEX; 345 345 else 346 346 *duplex = NIC_CM_HALF_DUPLEX; 347 347 348 348 uint32_t speed_bits = 349 349 (status >> STATUS_SPEED_SHIFT) & STATUS_SPEED_ALL; 350 350 351 351 if (speed_bits == STATUS_SPEED_10) 352 352 *speed = 10; … … 356 356 (speed_bits == STATUS_SPEED_1000B)) 357 357 *speed = 1000; 358 358 359 359 *role = NIC_ROLE_UNKNOWN; 360 360 return EOK; … … 364 364 { 365 365 fibril_mutex_lock(&e1000->ctrl_lock); 366 366 367 367 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL); 368 368 369 369 if (ctrl & CTRL_SLU) { 370 370 ctrl &= ~(CTRL_SLU); 371 371 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl); 372 372 fibril_mutex_unlock(&e1000->ctrl_lock); 373 373 374 374 async_usleep(10); 375 375 376 376 fibril_mutex_lock(&e1000->ctrl_lock); 377 377 ctrl = E1000_REG_READ(e1000, E1000_CTRL); … … 379 379 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl); 380 380 } 381 381 382 382 fibril_mutex_unlock(&e1000->ctrl_lock); 383 383 } … … 391 391 if ((speed != 10) && (speed != 100) && (speed != 1000)) 392 392 return EINVAL; 393 393 394 394 if ((duplex != NIC_CM_HALF_DUPLEX) && (duplex != NIC_CM_FULL_DUPLEX)) 395 395 return EINVAL; 396 396 397 397 e1000_t *e1000 = DRIVER_DATA_FUN(fun); 398 398 399 399 fibril_mutex_lock(&e1000->ctrl_lock); 400 400 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL); 401 401 402 402 ctrl |= CTRL_FRCSPD; 403 403 ctrl |= CTRL_FRCDPLX; 404 404 ctrl &= ~(CTRL_ASDE); 405 405 406 406 if (duplex == NIC_CM_FULL_DUPLEX) 407 407 ctrl |= CTRL_FD; 408 408 else 409 409 ctrl &= ~(CTRL_FD); 410 410 411 411 ctrl &= ~(CTRL_SPEED_MASK); 412 412 if (speed == 1000) … … 416 416 else 417 417 ctrl |= CTRL_SPEED_10 << CTRL_SPEED_SHIFT; 418 418 419 419 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl); 420 420 421 421 fibril_mutex_unlock(&e1000->ctrl_lock); 422 422 423 423 e1000_link_restart(e1000); 424 424 425 425 return EOK; 426 426 } … … 437 437 { 438 438 e1000_t *e1000 = DRIVER_DATA_FUN(fun); 439 439 440 440 fibril_mutex_lock(&e1000->ctrl_lock); 441 441 442 442 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL); 443 443 444 444 ctrl &= ~(CTRL_FRCSPD); 445 445 ctrl &= ~(CTRL_FRCDPLX); 446 446 ctrl |= CTRL_ASDE; 447 447 448 448 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl); 449 449 450 450 fibril_mutex_unlock(&e1000->ctrl_lock); 451 451 452 452 e1000_link_restart(e1000); 453 453 454 454 return EOK; 455 455 } … … 465 465 { 466 466 e1000_t *e1000 = DRIVER_DATA_FUN(fun); 467 467 468 468 fibril_mutex_lock(&e1000->ctrl_lock); 469 469 470 470 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL); 471 471 472 472 ctrl |= CTRL_FRCSPD; 473 473 ctrl |= CTRL_FRCDPLX; 474 474 ctrl &= ~(CTRL_ASDE); 475 475 476 476 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl); 477 477 478 478 fibril_mutex_unlock(&e1000->ctrl_lock); 479 479 480 480 e1000_link_restart(e1000); 481 481 482 482 return EOK; 483 483 } … … 504 504 { 505 505 e1000_t *e1000 = DRIVER_DATA_FUN(fun); 506 506 507 507 *mode = 0; 508 508 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL); 509 509 if (rctl & RCTL_SBP) 510 510 *mode = NIC_DEFECTIVE_BAD_CRC | NIC_DEFECTIVE_SHORT; 511 511 512 512 return EOK; 513 513 }; … … 526 526 e1000_t *e1000 = DRIVER_DATA_FUN(fun); 527 527 errno_t rc = EOK; 528 528 529 529 fibril_mutex_lock(&e1000->rx_lock); 530 530 531 531 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL); 532 532 bool short_mode = (mode & NIC_DEFECTIVE_SHORT ? true : false); 533 533 bool bad_mode = (mode & NIC_DEFECTIVE_BAD_CRC ? true : false); 534 534 535 535 if (short_mode && bad_mode) 536 536 rctl |= RCTL_SBP; … … 539 539 else 540 540 rc = ENOTSUP; 541 541 542 542 E1000_REG_WRITE(e1000, E1000_RCTL, rctl); 543 543 544 544 fibril_mutex_unlock(&e1000->rx_lock); 545 545 return rc; … … 563 563 uint8_t *mac4 = (uint8_t *) address->address + 4; 564 564 uint8_t *mac5 = (uint8_t *) address->address + 5; 565 565 566 566 uint32_t rah; 567 567 uint32_t ral; 568 568 569 569 ral = ((*mac3) << 24) | ((*mac2) << 16) | ((*mac1) << 8) | (*mac0); 570 570 rah = ((*mac5) << 8) | ((*mac4)); 571 571 572 572 if (set_av_bit) 573 573 rah |= RAH_AV; 574 574 else 575 575 rah |= E1000_REG_READ(e1000, E1000_RAH_ARRAY(position)) & RAH_AV; 576 576 577 577 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah); 578 578 E1000_REG_WRITE(e1000, E1000_RAL_ARRAY(position), ral); … … 605 605 ra_num++) 606 606 e1000_disable_receive_address(e1000, ra_num); 607 607 608 608 e1000->unicast_ra_count = 0; 609 609 } … … 618 618 unsigned int first_multicast_ra_num = 619 619 E1000_RECEIVE_ADDRESS - e1000->multicast_ra_count; 620 620 621 621 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1; 622 622 ra_num >= first_multicast_ra_num; 623 623 ra_num--) 624 624 e1000_disable_receive_address(e1000, ra_num); 625 625 626 626 e1000->multicast_ra_count = 0; 627 627 } … … 662 662 { 663 663 assert(addr_cnt <= get_free_unicast_address_count(e1000)); 664 664 665 665 nic_address_t *addr_iterator = (nic_address_t *) addr; 666 666 667 667 /* ra_num = 0 is primary address */ 668 668 for (unsigned int ra_num = 1; … … 685 685 { 686 686 assert(addr_cnt <= get_free_multicast_address_count(e1000)); 687 687 688 688 nic_address_t *addr_iterator = (nic_address_t *) addr; 689 689 690 690 unsigned int first_multicast_ra_num = E1000_RECEIVE_ADDRESS - addr_cnt; 691 691 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1; … … 832 832 e1000_t *e1000 = DRIVER_DATA_NIC(nic); 833 833 errno_t rc = EOK; 834 834 835 835 fibril_mutex_lock(&e1000->rx_lock); 836 836 837 837 switch (mode) { 838 838 case NIC_MULTICAST_BLOCKED: … … 866 866 break; 867 867 } 868 868 869 869 fibril_mutex_unlock(&e1000->rx_lock); 870 870 return rc; … … 886 886 e1000_t *e1000 = DRIVER_DATA_NIC(nic); 887 887 errno_t rc = EOK; 888 888 889 889 fibril_mutex_lock(&e1000->rx_lock); 890 890 891 891 switch (mode) { 892 892 case NIC_UNICAST_BLOCKED: … … 924 924 break; 925 925 } 926 926 927 927 fibril_mutex_unlock(&e1000->rx_lock); 928 928 return rc; … … 941 941 e1000_t *e1000 = DRIVER_DATA_NIC(nic); 942 942 errno_t rc = EOK; 943 943 944 944 fibril_mutex_lock(&e1000->rx_lock); 945 945 946 946 switch (mode) { 947 947 case NIC_BROADCAST_BLOCKED: … … 955 955 break; 956 956 } 957 957 958 958 fibril_mutex_unlock(&e1000->rx_lock); 959 959 return rc; … … 971 971 if (E1000_REG_READ(e1000, E1000_RCTL) & (RCTL_EN)) 972 972 return true; 973 973 974 974 return false; 975 975 } … … 1009 1009 { 1010 1010 e1000_t *e1000 = DRIVER_DATA_NIC(nic); 1011 1011 1012 1012 fibril_mutex_lock(&e1000->rx_lock); 1013 1013 1014 1014 if (vlan_mask) { 1015 1015 /* … … 1020 1020 if (rx_enabled) 1021 1021 e1000_disable_rx(e1000); 1022 1022 1023 1023 for (unsigned int i = 0; i < NIC_VLAN_BITMAP_SIZE; i += 4) { 1024 1024 uint32_t bitmap_part = … … 1029 1029 E1000_REG_WRITE(e1000, E1000_VFTA_ARRAY(i / 4), bitmap_part); 1030 1030 } 1031 1031 1032 1032 e1000_enable_vlan_filter(e1000); 1033 1033 if (rx_enabled) … … 1035 1035 } else 1036 1036 e1000_disable_vlan_filter(e1000); 1037 1037 1038 1038 fibril_mutex_unlock(&e1000->rx_lock); 1039 1039 } … … 1054 1054 if (tag & VLANTAG_CFI) 1055 1055 return ENOTSUP; 1056 1056 1057 1057 /* 1058 1058 * CTRL.VME is neccessary for both strip and add … … 1061 1061 if (!strip && add) 1062 1062 return ENOTSUP; 1063 1063 1064 1064 e1000_t *e1000 = DRIVER_DATA_FUN(fun); 1065 1065 1066 1066 e1000->vlan_tag = tag; 1067 1067 e1000->vlan_tag_add = add; 1068 1068 1069 1069 fibril_mutex_lock(&e1000->ctrl_lock); 1070 1070 1071 1071 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL); 1072 1072 if (strip) … … 1074 1074 else 1075 1075 ctrl &= ~CTRL_VME; 1076 1076 1077 1077 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl); 1078 1078 1079 1079 fibril_mutex_unlock(&e1000->ctrl_lock); 1080 1080 return EOK; … … 1092 1092 { 1093 1093 e1000_t *e1000 = DRIVER_DATA_NIC(nic); 1094 1094 1095 1095 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *) 1096 1096 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t)); 1097 1097 1098 1098 rx_descriptor->phys_addr = PTR_TO_U64(e1000->rx_frame_phys[offset]); 1099 1099 rx_descriptor->length = 0; … … 1114 1114 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *) 1115 1115 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t)); 1116 1116 1117 1117 rx_descriptor->length = 0; 1118 1118 rx_descriptor->checksum = 0; … … 1131 1131 { 1132 1132 e1000_t *e1000 = DRIVER_DATA_NIC(nic); 1133 1133 1134 1134 e1000_tx_descriptor_t *tx_descriptor = (e1000_tx_descriptor_t *) 1135 1135 (e1000->tx_ring_virt + offset * sizeof(e1000_tx_descriptor_t)); 1136 1136 1137 1137 tx_descriptor->phys_addr = 0; 1138 1138 tx_descriptor->length = 0; … … 1168 1168 { 1169 1169 e1000_t *e1000 = DRIVER_DATA_NIC(nic); 1170 1170 1171 1171 fibril_mutex_lock(&e1000->rx_lock); 1172 1172 1173 1173 uint32_t *tail_addr = E1000_REG_ADDR(e1000, E1000_RDT); 1174 1174 uint32_t next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT); 1175 1175 1176 1176 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *) 1177 1177 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t)); 1178 1178 1179 1179 while (rx_descriptor->status & 0x01) { 1180 1180 uint32_t frame_size = rx_descriptor->length - E1000_CRC_SIZE; 1181 1181 1182 1182 nic_frame_t *frame = nic_alloc_frame(nic, frame_size); 1183 1183 if (frame != NULL) { … … 1187 1187 ddf_msg(LVL_ERROR, "Memory allocation failed. Frame dropped."); 1188 1188 } 1189 1189 1190 1190 e1000_fill_new_rx_descriptor(nic, next_tail); 1191 1191 1192 1192 *tail_addr = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT); 1193 1193 next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT); 1194 1194 1195 1195 rx_descriptor = (e1000_rx_descriptor_t *) 1196 1196 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t)); 1197 1197 } 1198 1198 1199 1199 fibril_mutex_unlock(&e1000->rx_lock); 1200 1200 } … … 1247 1247 nic_t *nic = NIC_DATA_DEV(dev); 1248 1248 e1000_t *e1000 = DRIVER_DATA_NIC(nic); 1249 1249 1250 1250 e1000_interrupt_handler_impl(nic, icr); 1251 1251 e1000_enable_interrupts(e1000); … … 1267 1267 { 1268 1268 e1000_t *e1000 = DRIVER_DATA_NIC(nic); 1269 1269 1270 1270 /* Lock the mutex in whole driver while working with global structure */ 1271 1271 fibril_mutex_lock(&irq_reg_mutex); 1272 1272 1273 1273 e1000_irq_code.ranges[0].base = (uintptr_t) e1000->reg_base_phys; 1274 1274 e1000_irq_code.cmds[0].addr = e1000->reg_base_phys + E1000_ICR; 1275 1275 e1000_irq_code.cmds[2].addr = e1000->reg_base_phys + E1000_IMC; 1276 1276 1277 1277 errno_t rc = register_interrupt_handler(nic_get_ddf_dev(nic), e1000->irq, 1278 1278 e1000_interrupt_handler, &e1000_irq_code, handle); 1279 1279 1280 1280 fibril_mutex_unlock(&irq_reg_mutex); 1281 1281 return rc; … … 1290 1290 { 1291 1291 assert(nic); 1292 1292 1293 1293 e1000_t *e1000 = nic_get_specific(nic); 1294 1294 assert(e1000); 1295 1295 1296 1296 uint32_t icr = E1000_REG_READ(e1000, E1000_ICR); 1297 1297 e1000_interrupt_handler_impl(nic, icr); … … 1323 1323 { 1324 1324 assert(nic); 1325 1325 1326 1326 e1000_t *e1000 = nic_get_specific(nic); 1327 1327 assert(e1000); 1328 1328 1329 1329 switch (mode) { 1330 1330 case NIC_POLL_IMMEDIATE: … … 1344 1344 return ENOTSUP; 1345 1345 } 1346 1346 1347 1347 return EOK; 1348 1348 } … … 1357 1357 E1000_REG_WRITE(e1000, E1000_RDLEN, E1000_RX_FRAME_COUNT * 16); 1358 1358 E1000_REG_WRITE(e1000, E1000_RDH, 0); 1359 1359 1360 1360 /* It is not posible to let HW use all descriptors */ 1361 1361 E1000_REG_WRITE(e1000, E1000_RDT, E1000_RX_FRAME_COUNT - 1); 1362 1362 1363 1363 /* Set Broadcast Enable Bit */ 1364 1364 E1000_REG_WRITE(e1000, E1000_RCTL, RCTL_BAM); … … 1377 1377 e1000_t *e1000 = DRIVER_DATA_NIC(nic); 1378 1378 fibril_mutex_lock(&e1000->rx_lock); 1379 1379 1380 1380 e1000->rx_ring_virt = AS_AREA_ANY; 1381 1381 errno_t rc = dmamem_map_anonymous( … … 1385 1385 if (rc != EOK) 1386 1386 return rc; 1387 1387 1388 1388 E1000_REG_WRITE(e1000, E1000_RDBAH, 1389 1389 (uint32_t) (PTR_TO_U64(e1000->rx_ring_phys) >> 32)); 1390 1390 E1000_REG_WRITE(e1000, E1000_RDBAL, 1391 1391 (uint32_t) PTR_TO_U64(e1000->rx_ring_phys)); 1392 1392 1393 1393 e1000->rx_frame_phys = (uintptr_t *) 1394 1394 calloc(E1000_RX_FRAME_COUNT, sizeof(uintptr_t)); … … 1399 1399 goto error; 1400 1400 } 1401 1401 1402 1402 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++) { 1403 1403 uintptr_t frame_phys; 1404 1404 void *frame_virt = AS_AREA_ANY; 1405 1405 1406 1406 rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE, 1407 1407 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0, … … 1409 1409 if (rc != EOK) 1410 1410 goto error; 1411 1411 1412 1412 e1000->rx_frame_phys[i] = frame_phys; 1413 1413 e1000->rx_frame_virt[i] = frame_virt; 1414 1414 } 1415 1415 1416 1416 /* Write descriptor */ 1417 1417 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++) 1418 1418 e1000_fill_new_rx_descriptor(nic, i); 1419 1419 1420 1420 e1000_initialize_rx_registers(e1000); 1421 1421 1422 1422 fibril_mutex_unlock(&e1000->rx_lock); 1423 1423 return EOK; 1424 1424 1425 1425 error: 1426 1426 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++) { … … 1431 1431 } 1432 1432 } 1433 1433 1434 1434 if (e1000->rx_frame_phys != NULL) { 1435 1435 free(e1000->rx_frame_phys); 1436 1436 e1000->rx_frame_phys = NULL; 1437 1437 } 1438 1438 1439 1439 if (e1000->rx_frame_virt != NULL) { 1440 1440 free(e1000->rx_frame_virt); 1441 1441 e1000->rx_frame_virt = NULL; 1442 1442 } 1443 1443 1444 1444 return rc; 1445 1445 } … … 1453 1453 { 1454 1454 e1000_t *e1000 = DRIVER_DATA_NIC(nic); 1455 1455 1456 1456 /* Write descriptor */ 1457 1457 for (unsigned int offset = 0; offset < E1000_RX_FRAME_COUNT; offset++) { … … 1460 1460 e1000->rx_frame_virt[offset] = NULL; 1461 1461 } 1462 1462 1463 1463 free(e1000->rx_frame_virt); 1464 1464 1465 1465 e1000->rx_frame_phys = NULL; 1466 1466 e1000->rx_frame_virt = NULL; 1467 1467 1468 1468 dmamem_unmap_anonymous(e1000->rx_ring_virt); 1469 1469 } … … 1550 1550 E1000_REG_WRITE(e1000, E1000_TDH, 0); 1551 1551 E1000_REG_WRITE(e1000, E1000_TDT, 0); 1552 1552 1553 1553 E1000_REG_WRITE(e1000, E1000_TIPG, 1554 1554 10 << TIPG_IPGT_SHIFT | 1555 1555 8 << TIPG_IPGR1_SHIFT | 1556 1556 6 << TIPG_IPGR2_SHIFT); 1557 1557 1558 1558 E1000_REG_WRITE(e1000, E1000_TCTL, 1559 1559 0x0F << TCTL_CT_SHIFT /* Collision Threshold */ | … … 1570 1570 { 1571 1571 size_t i; 1572 1572 1573 1573 fibril_mutex_lock(&e1000->tx_lock); 1574 1574 1575 1575 e1000->tx_ring_phys = 0; 1576 1576 e1000->tx_ring_virt = AS_AREA_ANY; 1577 1577 1578 1578 e1000->tx_frame_phys = NULL; 1579 1579 e1000->tx_frame_virt = NULL; 1580 1580 1581 1581 errno_t rc = dmamem_map_anonymous( 1582 1582 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t), … … 1585 1585 if (rc != EOK) 1586 1586 goto error; 1587 1587 1588 1588 memset(e1000->tx_ring_virt, 0, 1589 1589 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t)); 1590 1590 1591 1591 e1000->tx_frame_phys = (uintptr_t *) 1592 1592 calloc(E1000_TX_FRAME_COUNT, sizeof(uintptr_t)); … … 1598 1598 goto error; 1599 1599 } 1600 1600 1601 1601 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) { 1602 1602 e1000->tx_frame_virt[i] = AS_AREA_ANY; … … 1607 1607 goto error; 1608 1608 } 1609 1609 1610 1610 E1000_REG_WRITE(e1000, E1000_TDBAH, 1611 1611 (uint32_t) (PTR_TO_U64(e1000->tx_ring_phys) >> 32)); 1612 1612 E1000_REG_WRITE(e1000, E1000_TDBAL, 1613 1613 (uint32_t) PTR_TO_U64(e1000->tx_ring_phys)); 1614 1614 1615 1615 e1000_initialize_tx_registers(e1000); 1616 1616 1617 1617 fibril_mutex_unlock(&e1000->tx_lock); 1618 1618 return EOK; 1619 1619 1620 1620 error: 1621 1621 if (e1000->tx_ring_virt != NULL) { … … 1623 1623 e1000->tx_ring_virt = NULL; 1624 1624 } 1625 1625 1626 1626 if ((e1000->tx_frame_phys != NULL) && (e1000->tx_frame_virt != NULL)) { 1627 1627 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) { … … 1633 1633 } 1634 1634 } 1635 1635 1636 1636 if (e1000->tx_frame_phys != NULL) { 1637 1637 free(e1000->tx_frame_phys); 1638 1638 e1000->tx_frame_phys = NULL; 1639 1639 } 1640 1640 1641 1641 if (e1000->tx_frame_virt != NULL) { 1642 1642 free(e1000->tx_frame_virt); 1643 1643 e1000->tx_frame_virt = NULL; 1644 1644 } 1645 1645 1646 1646 return rc; 1647 1647 } … … 1655 1655 { 1656 1656 size_t i; 1657 1657 1658 1658 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) { 1659 1659 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]); … … 1661 1661 e1000->tx_frame_virt[i] = NULL; 1662 1662 } 1663 1663 1664 1664 if (e1000->tx_frame_phys != NULL) { 1665 1665 free(e1000->tx_frame_phys); 1666 1666 e1000->tx_frame_phys = NULL; 1667 1667 } 1668 1668 1669 1669 if (e1000->tx_frame_virt != NULL) { 1670 1670 free(e1000->tx_frame_virt); 1671 1671 e1000->tx_frame_virt = NULL; 1672 1672 } 1673 1673 1674 1674 dmamem_unmap_anonymous(e1000->tx_ring_virt); 1675 1675 } … … 1721 1721 { 1722 1722 e1000_t *e1000 = DRIVER_DATA_NIC(nic); 1723 1723 1724 1724 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_RST); 1725 1725 1726 1726 /* Wait for the reset */ 1727 1727 async_usleep(20); 1728 1728 1729 1729 /* check if RST_BIT cleared */ 1730 1730 if (E1000_REG_READ(e1000, E1000_CTRL) & (CTRL_RST)) 1731 1731 return EINVAL; 1732 1732 1733 1733 e1000_initialize_registers(e1000); 1734 1734 e1000_initialize_rx_registers(e1000); … … 1737 1737 e1000_initialize_filters(e1000); 1738 1738 e1000_initialize_vlan(e1000); 1739 1739 1740 1740 return EOK; 1741 1741 } … … 1752 1752 { 1753 1753 assert(nic); 1754 1754 1755 1755 e1000_t *e1000 = DRIVER_DATA_NIC(nic); 1756 1756 1757 1757 fibril_mutex_lock(&e1000->rx_lock); 1758 1758 fibril_mutex_lock(&e1000->tx_lock); 1759 1759 fibril_mutex_lock(&e1000->ctrl_lock); 1760 1760 1761 1761 e1000_enable_interrupts(e1000); 1762 1762 1763 1763 errno_t rc = hw_res_enable_interrupt(e1000->parent_sess, e1000->irq); 1764 1764 if (rc != EOK) { … … 1769 1769 return rc; 1770 1770 } 1771 1771 1772 1772 e1000_clear_rx_ring(e1000); 1773 1773 e1000_enable_rx(e1000); 1774 1774 1775 1775 e1000_clear_tx_ring(nic); 1776 1776 e1000_enable_tx(e1000); 1777 1777 1778 1778 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL); 1779 1779 ctrl |= CTRL_SLU; 1780 1780 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl); 1781 1781 1782 1782 fibril_mutex_unlock(&e1000->ctrl_lock); 1783 1783 fibril_mutex_unlock(&e1000->tx_lock); 1784 1784 fibril_mutex_unlock(&e1000->rx_lock); 1785 1785 1786 1786 return EOK; 1787 1787 } … … 1798 1798 { 1799 1799 e1000_t *e1000 = DRIVER_DATA_NIC(nic); 1800 1800 1801 1801 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL); 1802 1802 ctrl &= ~CTRL_SLU; 1803 1803 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl); 1804 1804 1805 1805 e1000_disable_tx(e1000); 1806 1806 e1000_disable_rx(e1000); 1807 1807 1808 1808 hw_res_disable_interrupt(e1000->parent_sess, e1000->irq); 1809 1809 e1000_disable_interrupts(e1000); 1810 1810 1811 1811 /* 1812 1812 * Wait for the for the end of all data … … 1814 1814 */ 1815 1815 async_usleep(100); 1816 1816 1817 1817 return EOK; 1818 1818 } … … 1829 1829 { 1830 1830 e1000_t *e1000 = DRIVER_DATA_NIC(nic); 1831 1831 1832 1832 fibril_mutex_lock(&e1000->rx_lock); 1833 1833 fibril_mutex_lock(&e1000->tx_lock); 1834 1834 fibril_mutex_lock(&e1000->ctrl_lock); 1835 1835 1836 1836 errno_t rc = e1000_on_down_unlocked(nic); 1837 1837 1838 1838 fibril_mutex_unlock(&e1000->ctrl_lock); 1839 1839 fibril_mutex_unlock(&e1000->tx_lock); 1840 1840 fibril_mutex_unlock(&e1000->rx_lock); 1841 1841 1842 1842 return rc; 1843 1843 } … … 1854 1854 { 1855 1855 e1000_t *e1000 = DRIVER_DATA_NIC(nic); 1856 1856 1857 1857 fibril_mutex_lock(&e1000->rx_lock); 1858 1858 fibril_mutex_lock(&e1000->tx_lock); 1859 1859 fibril_mutex_lock(&e1000->ctrl_lock); 1860 1860 1861 1861 errno_t rc = e1000_on_down_unlocked(nic); 1862 1862 if (rc == EOK) 1863 1863 rc = e1000_reset(nic); 1864 1864 1865 1865 fibril_mutex_unlock(&e1000->ctrl_lock); 1866 1866 fibril_mutex_unlock(&e1000->tx_lock); 1867 1867 fibril_mutex_unlock(&e1000->rx_lock); 1868 1868 1869 1869 return rc; 1870 1870 } … … 1880 1880 if (!nic) 1881 1881 return NULL; 1882 1882 1883 1883 e1000_t *e1000 = malloc(sizeof(e1000_t)); 1884 1884 if (!e1000) { … … 1886 1886 return NULL; 1887 1887 } 1888 1888 1889 1889 memset(e1000, 0, sizeof(e1000_t)); 1890 1890 e1000->dev = dev; 1891 1891 1892 1892 nic_set_specific(nic, e1000); 1893 1893 nic_set_send_frame_handler(nic, e1000_send_frame); … … 1898 1898 e1000_on_broadcast_mode_change, NULL, e1000_on_vlan_mask_change); 1899 1899 nic_set_poll_handlers(nic, e1000_poll_mode_change, e1000_poll); 1900 1900 1901 1901 fibril_mutex_initialize(&e1000->ctrl_lock); 1902 1902 fibril_mutex_initialize(&e1000->rx_lock); 1903 1903 fibril_mutex_initialize(&e1000->tx_lock); 1904 1904 fibril_mutex_initialize(&e1000->eeprom_lock); 1905 1905 1906 1906 return e1000; 1907 1907 } … … 1915 1915 { 1916 1916 assert(dev); 1917 1917 1918 1918 if (ddf_dev_data_get(dev) != NULL) 1919 1919 nic_unbind_and_destroy(dev); … … 1928 1928 { 1929 1929 assert(dev); 1930 1930 1931 1931 e1000_delete_dev_data(dev); 1932 1932 } … … 1947 1947 { 1948 1948 e1000_t *e1000 = DRIVER_DATA_DEV(dev); 1949 1949 1950 1950 if (hw_resources->irqs.count != 1) 1951 1951 return EINVAL; 1952 1952 1953 1953 e1000->irq = hw_resources->irqs.irqs[0]; 1954 1954 e1000->reg_base_phys = 1955 1955 MEMADDR_TO_PTR(RNGABS(hw_resources->mem_ranges.ranges[0])); 1956 1956 1957 1957 return EOK; 1958 1958 } … … 1972 1972 assert(dev != NULL); 1973 1973 assert(NIC_DATA_DEV(dev) != NULL); 1974 1974 1975 1975 hw_res_list_parsed_t hw_res_parsed; 1976 1976 hw_res_list_parsed_init(&hw_res_parsed); 1977 1977 1978 1978 /* Get hw resources form parent driver */ 1979 1979 errno_t rc = nic_get_resources(NIC_DATA_DEV(dev), &hw_res_parsed); 1980 1980 if (rc != EOK) 1981 1981 return rc; 1982 1982 1983 1983 /* Fill resources information to the device */ 1984 1984 rc = e1000_fill_resource_info(dev, &hw_res_parsed); 1985 1985 hw_res_list_parsed_clean(&hw_res_parsed); 1986 1986 1987 1987 return rc; 1988 1988 } … … 2004 2004 return ENOMEM; 2005 2005 } 2006 2006 2007 2007 e1000->parent_sess = ddf_dev_parent_sess_get(dev); 2008 2008 if (e1000->parent_sess == NULL) { … … 2010 2010 return EIO; 2011 2011 } 2012 2012 2013 2013 /* Obtain and fill hardware resources info */ 2014 2014 errno_t rc = e1000_get_resource_info(dev); … … 2018 2018 return rc; 2019 2019 } 2020 2020 2021 2021 uint16_t device_id; 2022 2022 rc = pci_config_space_read_16(ddf_dev_parent_sess_get(dev), PCI_DEVICE_ID, … … 2027 2027 return rc; 2028 2028 } 2029 2029 2030 2030 e1000_board_t board; 2031 2031 switch (device_id) { … … 2077 2077 return ENOTSUP; 2078 2078 } 2079 2079 2080 2080 switch (board) { 2081 2081 case E1000_82540: … … 2098 2098 break; 2099 2099 } 2100 2100 2101 2101 return EOK; 2102 2102 } … … 2113 2113 { 2114 2114 e1000_t *e1000 = DRIVER_DATA_DEV(dev); 2115 2115 2116 2116 errno_t rc = pio_enable(e1000->reg_base_phys, 8 * PAGE_SIZE, 2117 2117 &e1000->reg_base_virt); 2118 2118 if (rc != EOK) 2119 2119 return EADDRNOTAVAIL; 2120 2120 2121 2121 return EOK; 2122 2122 } … … 2130 2130 { 2131 2131 ddf_fun_t *fun; 2132 2132 2133 2133 /* Initialize device structure for E1000 */ 2134 2134 errno_t rc = e1000_device_initialize(dev); 2135 2135 if (rc != EOK) 2136 2136 return rc; 2137 2137 2138 2138 /* Device initialization */ 2139 2139 nic_t *nic = ddf_dev_data_get(dev); 2140 2140 e1000_t *e1000 = DRIVER_DATA_NIC(nic); 2141 2141 2142 2142 /* Map registers */ 2143 2143 rc = e1000_pio_enable(dev); 2144 2144 if (rc != EOK) 2145 2145 goto err_destroy; 2146 2146 2147 2147 e1000_initialize_registers(e1000); 2148 2148 rc = e1000_initialize_tx_structure(e1000); 2149 2149 if (rc != EOK) 2150 2150 goto err_pio; 2151 2151 2152 2152 fibril_mutex_lock(&e1000->rx_lock); 2153 2153 2154 2154 e1000_fill_mac_from_eeprom(e1000); 2155 2155 e1000_initialize_filters(e1000); 2156 2156 2157 2157 fibril_mutex_unlock(&e1000->rx_lock); 2158 2158 2159 2159 e1000_initialize_vlan(e1000); 2160 2160 2161 2161 fun = ddf_fun_create(nic_get_ddf_dev(nic), fun_exposed, "port0"); 2162 2162 if (fun == NULL) … … 2164 2164 nic_set_ddf_fun(nic, fun); 2165 2165 ddf_fun_set_ops(fun, &e1000_dev_ops); 2166 2166 2167 2167 int irq_cap; 2168 2168 rc = e1000_register_int_handler(nic, &irq_cap); … … 2170 2170 goto err_fun_create; 2171 2171 } 2172 2172 2173 2173 rc = e1000_initialize_rx_structure(nic); 2174 2174 if (rc != EOK) 2175 2175 goto err_irq; 2176 2176 2177 2177 nic_address_t e1000_address; 2178 2178 e1000_get_address(e1000, &e1000_address); … … 2180 2180 if (rc != EOK) 2181 2181 goto err_rx_structure; 2182 2182 2183 2183 struct timeval period; 2184 2184 period.tv_sec = 0; … … 2187 2187 if (rc != EOK) 2188 2188 goto err_rx_structure; 2189 2189 2190 2190 rc = ddf_fun_bind(fun); 2191 2191 if (rc != EOK) 2192 2192 goto err_fun_bind; 2193 2193 2194 2194 rc = ddf_fun_add_to_category(fun, DEVICE_CATEGORY_NIC); 2195 2195 if (rc != EOK) 2196 2196 goto err_add_to_cat; 2197 2197 2198 2198 return EOK; 2199 2199 2200 2200 err_add_to_cat: 2201 2201 ddf_fun_unbind(fun); … … 2230 2230 { 2231 2231 fibril_mutex_lock(&e1000->eeprom_lock); 2232 2232 2233 2233 /* Write address and START bit to EERD register */ 2234 2234 uint32_t write_data = e1000->info.eerd_start | … … 2236 2236 e1000->info.eerd_address_offset); 2237 2237 E1000_REG_WRITE(e1000, E1000_EERD, write_data); 2238 2238 2239 2239 uint32_t eerd = E1000_REG_READ(e1000, E1000_EERD); 2240 2240 while ((eerd & e1000->info.eerd_done) == 0) { … … 2242 2242 eerd = E1000_REG_READ(e1000, E1000_EERD); 2243 2243 } 2244 2244 2245 2245 fibril_mutex_unlock(&e1000->eeprom_lock); 2246 2246 2247 2247 return (uint16_t) (eerd >> e1000->info.eerd_data_offset); 2248 2248 } … … 2261 2261 { 2262 2262 fibril_mutex_lock(&e1000->rx_lock); 2263 2263 2264 2264 uint8_t *mac0_dest = (uint8_t *) address->address; 2265 2265 uint8_t *mac1_dest = (uint8_t *) address->address + 1; … … 2268 2268 uint8_t *mac4_dest = (uint8_t *) address->address + 4; 2269 2269 uint8_t *mac5_dest = (uint8_t *) address->address + 5; 2270 2270 2271 2271 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0)); 2272 2272 uint32_t ral = E1000_REG_READ(e1000, E1000_RAL_ARRAY(0)); 2273 2273 2274 2274 *mac0_dest = (uint8_t) ral; 2275 2275 *mac1_dest = (uint8_t) (ral >> 8); … … 2278 2278 *mac4_dest = (uint8_t) rah; 2279 2279 *mac5_dest = (uint8_t) (rah >> 8); 2280 2280 2281 2281 fibril_mutex_unlock(&e1000->rx_lock); 2282 2282 return EOK; … … 2295 2295 nic_t *nic = NIC_DATA_FUN(fun); 2296 2296 e1000_t *e1000 = DRIVER_DATA_NIC(nic); 2297 2297 2298 2298 fibril_mutex_lock(&e1000->rx_lock); 2299 2299 fibril_mutex_lock(&e1000->tx_lock); 2300 2300 2301 2301 errno_t rc = nic_report_address(nic, addr); 2302 2302 if (rc == EOK) 2303 2303 e1000_write_receive_address(e1000, 0, addr, false); 2304 2304 2305 2305 fibril_mutex_unlock(&e1000->tx_lock); 2306 2306 fibril_mutex_unlock(&e1000->rx_lock); 2307 2307 2308 2308 return rc; 2309 2309 } … … 2315 2315 uint16_t *mac2_dest = (uint16_t *) (address->address + 2); 2316 2316 uint16_t *mac4_dest = (uint16_t *) (address->address + 4); 2317 2317 2318 2318 *mac0_dest = e1000_eeprom_read(e1000, 0); 2319 2319 *mac2_dest = e1000_eeprom_read(e1000, 1); … … 2334 2334 { 2335 2335 assert(nic); 2336 2336 2337 2337 e1000_t *e1000 = DRIVER_DATA_NIC(nic); 2338 2338 fibril_mutex_lock(&e1000->tx_lock); 2339 2339 2340 2340 uint32_t tdt = E1000_REG_READ(e1000, E1000_TDT); 2341 2341 e1000_tx_descriptor_t *tx_descriptor_addr = (e1000_tx_descriptor_t *) 2342 2342 (e1000->tx_ring_virt + tdt * sizeof(e1000_tx_descriptor_t)); 2343 2343 2344 2344 bool descriptor_available = false; 2345 2345 2346 2346 /* Descriptor never used */ 2347 2347 if (tx_descriptor_addr->length == 0) 2348 2348 descriptor_available = true; 2349 2349 2350 2350 /* Descriptor done */ 2351 2351 if (tx_descriptor_addr->status & TXDESCRIPTOR_STATUS_DD) 2352 2352 descriptor_available = true; 2353 2353 2354 2354 if (!descriptor_available) { 2355 2355 /* Frame lost */ … … 2357 2357 return; 2358 2358 } 2359 2359 2360 2360 memcpy(e1000->tx_frame_virt[tdt], data, size); 2361 2361 2362 2362 tx_descriptor_addr->phys_addr = PTR_TO_U64(e1000->tx_frame_phys[tdt]); 2363 2363 tx_descriptor_addr->length = size; 2364 2364 2365 2365 /* 2366 2366 * Report status to STATUS.DD (descriptor done), … … 2370 2370 TXDESCRIPTOR_COMMAND_IFCS | 2371 2371 TXDESCRIPTOR_COMMAND_EOP; 2372 2372 2373 2373 tx_descriptor_addr->checksum_offset = 0; 2374 2374 tx_descriptor_addr->status = 0; … … 2378 2378 } else 2379 2379 tx_descriptor_addr->special = 0; 2380 2380 2381 2381 tx_descriptor_addr->checksum_start_field = 0; 2382 2382 2383 2383 tdt++; 2384 2384 if (tdt == E1000_TX_FRAME_COUNT) 2385 2385 tdt = 0; 2386 2386 2387 2387 E1000_REG_WRITE(e1000, E1000_TDT, tdt); 2388 2388 2389 2389 fibril_mutex_unlock(&e1000->tx_lock); 2390 2390 } … … 2393 2393 { 2394 2394 printf("%s: HelenOS E1000 network adapter driver\n", NAME); 2395 2395 2396 2396 if (nic_driver_init(NAME) != EOK) 2397 2397 return 1; 2398 2398 2399 2399 nic_driver_implement(&e1000_driver_ops, &e1000_dev_ops, 2400 2400 &e1000_nic_iface); 2401 2401 2402 2402 ddf_log_init(NAME); 2403 2403 return ddf_driver_main(&e1000_driver);
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