Changes in uspace/drv/nic/ne2k/dp8390.c [5a6cc679:a35b458] in mainline
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uspace/drv/nic/ne2k/dp8390.c
r5a6cc679 ra35b458 74 74 /** Copy of RSR */ 75 75 uint8_t status; 76 76 77 77 /** Pointer to next frame */ 78 78 uint8_t next; 79 79 80 80 /** Receive Byte Count Low */ 81 81 uint8_t rbcl; 82 82 83 83 /** Receive Byte Count High */ 84 84 uint8_t rbch; … … 95 95 { 96 96 size_t i; 97 97 98 98 for (i = 0; (i << 1) < size; i++) 99 99 *((uint16_t *) buf + i) = pio_read_16((ioport16_t *) (port)); … … 110 110 { 111 111 size_t i; 112 112 113 113 for (i = 0; (i << 1) < size; i++) 114 114 pio_write_16((ioport16_t *) port, *((uint16_t *) buf + i)); … … 118 118 { 119 119 size_t esize = size & ~1; 120 120 121 121 pio_write_8(ne2k->port + DP_RBCR0, esize & 0xff); 122 122 pio_write_8(ne2k->port + DP_RBCR1, (esize >> 8) & 0xff); … … 124 124 pio_write_8(ne2k->port + DP_RSAR1, (addr >> 8) & 0xff); 125 125 pio_write_8(ne2k->port + DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA); 126 126 127 127 if (esize != 0) { 128 128 pio_read_buf_16(ne2k->data_port, buf, esize); … … 130 130 buf += esize; 131 131 } 132 132 133 133 if (size) { 134 134 assert(size == 1); 135 135 136 136 uint16_t word = pio_read_16(ne2k->data_port); 137 137 memcpy(buf, &word, 1); … … 143 143 size_t esize_ru = (size + 1) & ~1; 144 144 size_t esize = size & ~1; 145 145 146 146 pio_write_8(ne2k->port + DP_RBCR0, esize_ru & 0xff); 147 147 pio_write_8(ne2k->port + DP_RBCR1, (esize_ru >> 8) & 0xff); … … 149 149 pio_write_8(ne2k->port + DP_RSAR1, (addr >> 8) & 0xff); 150 150 pio_write_8(ne2k->port + DP_CR, CR_DM_RW | CR_PS_P0 | CR_STA); 151 151 152 152 if (esize != 0) { 153 153 pio_write_buf_16(ne2k->data_port, buf, esize); … … 155 155 buf += esize; 156 156 } 157 157 158 158 if (size) { 159 159 assert(size == 1); 160 160 161 161 uint16_t word = 0; 162 162 163 163 memcpy(&word, buf, 1); 164 164 pio_write_16(ne2k->data_port, word); … … 169 169 { 170 170 unsigned int i; 171 171 172 172 /* Reset the ethernet card */ 173 173 uint8_t val = pio_read_8(ne2k->port + NE2K_RESET); … … 175 175 pio_write_8(ne2k->port + NE2K_RESET, val); 176 176 async_usleep(2000); 177 177 178 178 /* Reset the DP8390 */ 179 179 pio_write_8(ne2k->port + DP_CR, CR_STP | CR_DM_ABORT); … … 197 197 { 198 198 unsigned int i; 199 199 200 200 ne2k_init(ne2k); 201 201 202 202 /* Check if the DP8390 is really there */ 203 203 uint8_t val = pio_read_8(ne2k->port + DP_CR); 204 204 if ((val & (CR_STP | CR_TXP | CR_DM_ABORT)) != (CR_STP | CR_DM_ABORT)) 205 205 return EXDEV; 206 206 207 207 /* Disable the receiver and init TCR and DCR */ 208 208 pio_write_8(ne2k->port + DP_RCR, RCR_MON); 209 209 pio_write_8(ne2k->port + DP_TCR, TCR_NORMAL); 210 210 pio_write_8(ne2k->port + DP_DCR, DCR_WORDWIDE | DCR_8BYTES | DCR_BMS); 211 211 212 212 /* Setup a transfer to get the MAC address */ 213 213 pio_write_8(ne2k->port + DP_RBCR0, ETH_ADDR << 1); … … 216 216 pio_write_8(ne2k->port + DP_RSAR1, 0); 217 217 pio_write_8(ne2k->port + DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA); 218 218 219 219 for (i = 0; i < ETH_ADDR; i++) 220 220 ne2k->mac.address[i] = pio_read_16(ne2k->data_port); 221 221 222 222 return EOK; 223 223 } … … 226 226 { 227 227 memcpy(&ne2k->mac, address, sizeof(nic_address_t)); 228 228 229 229 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_DM_ABORT | CR_STP); 230 230 231 231 pio_write_8(ne2k->port + DP_RBCR0, ETH_ADDR << 1); 232 232 pio_write_8(ne2k->port + DP_RBCR1, 0); … … 254 254 if (!ne2k->probed) 255 255 return EXDEV; 256 256 257 257 ne2k_init(ne2k); 258 258 259 259 /* 260 260 * Setup send queue. Use the first … … 266 266 fibril_mutex_initialize(&ne2k->sq_mutex); 267 267 fibril_condvar_initialize(&ne2k->sq_cv); 268 268 269 269 /* 270 270 * Setup receive ring buffer. Use all the rest … … 275 275 ne2k->start_page = ne2k->sq.page + SQ_PAGES; 276 276 ne2k->stop_page = ne2k->sq.page + NE2K_SIZE / DP_PAGE; 277 277 278 278 /* 279 279 * Initialization of the DP8390 following the mandatory procedure … … 281 281 * Controller", National Semiconductor, July 1995, Page 29). 282 282 */ 283 283 284 284 /* Step 1: */ 285 285 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_STP | CR_DM_ABORT); 286 286 287 287 /* Step 2: */ 288 288 pio_write_8(ne2k->port + DP_DCR, DCR_WORDWIDE | DCR_8BYTES | DCR_BMS); 289 289 290 290 /* Step 3: */ 291 291 pio_write_8(ne2k->port + DP_RBCR0, 0); 292 292 pio_write_8(ne2k->port + DP_RBCR1, 0); 293 293 294 294 /* Step 4: */ 295 295 pio_write_8(ne2k->port + DP_RCR, ne2k->receive_configuration); 296 296 297 297 /* Step 5: */ 298 298 pio_write_8(ne2k->port + DP_TCR, TCR_INTERNAL); 299 299 300 300 /* Step 6: */ 301 301 pio_write_8(ne2k->port + DP_BNRY, ne2k->start_page); 302 302 pio_write_8(ne2k->port + DP_PSTART, ne2k->start_page); 303 303 pio_write_8(ne2k->port + DP_PSTOP, ne2k->stop_page); 304 304 305 305 /* Step 7: */ 306 306 pio_write_8(ne2k->port + DP_ISR, 0xff); 307 307 308 308 /* Step 8: */ 309 309 pio_write_8(ne2k->port + DP_IMR, 310 310 IMR_PRXE | IMR_PTXE | IMR_RXEE | IMR_TXEE | IMR_OVWE | IMR_CNTE); 311 311 312 312 /* Step 9: */ 313 313 pio_write_8(ne2k->port + DP_CR, CR_PS_P1 | CR_DM_ABORT | CR_STP); 314 314 315 315 pio_write_8(ne2k->port + DP_PAR0, ne2k->mac.address[0]); 316 316 pio_write_8(ne2k->port + DP_PAR1, ne2k->mac.address[1]); … … 319 319 pio_write_8(ne2k->port + DP_PAR4, ne2k->mac.address[4]); 320 320 pio_write_8(ne2k->port + DP_PAR5, ne2k->mac.address[5]); 321 321 322 322 pio_write_8(ne2k->port + DP_MAR0, 0); 323 323 pio_write_8(ne2k->port + DP_MAR1, 0); … … 328 328 pio_write_8(ne2k->port + DP_MAR6, 0); 329 329 pio_write_8(ne2k->port + DP_MAR7, 0); 330 330 331 331 pio_write_8(ne2k->port + DP_CURR, ne2k->start_page + 1); 332 332 333 333 /* Step 10: */ 334 334 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_DM_ABORT | CR_STA); 335 335 336 336 /* Step 11: */ 337 337 pio_write_8(ne2k->port + DP_TCR, TCR_NORMAL); 338 338 339 339 /* Reset counters by reading */ 340 340 pio_read_8(ne2k->port + DP_CNTR0); 341 341 pio_read_8(ne2k->port + DP_CNTR1); 342 342 pio_read_8(ne2k->port + DP_CNTR2); 343 343 344 344 /* Finish the initialization */ 345 345 ne2k->up = true; … … 415 415 416 416 fibril_mutex_lock(&ne2k->sq_mutex); 417 417 418 418 while (ne2k->sq.dirty) { 419 419 fibril_condvar_wait(&ne2k->sq_cv, &ne2k->sq_mutex); 420 420 } 421 421 422 422 if ((size < ETH_MIN_PACK_SIZE) || (size > ETH_MAX_PACK_SIZE_TAGGED)) { 423 423 fibril_mutex_unlock(&ne2k->sq_mutex); … … 446 446 if (frame == NULL) 447 447 return NULL; 448 448 449 449 memset(frame->data, 0, length); 450 450 uint8_t last = page + length / DP_PAGE; 451 451 452 452 if (last >= ne2k->stop_page) { 453 453 size_t left = (ne2k->stop_page - page) * DP_PAGE … … 481 481 //TODO: isn't some locking necessary here? 482 482 uint8_t boundary = pio_read_8(ne2k->port + DP_BNRY) + 1; 483 483 484 484 if (boundary == ne2k->stop_page) 485 485 boundary = ne2k->start_page; 486 486 487 487 pio_write_8(ne2k->port + DP_CR, CR_PS_P1 | CR_STA); 488 488 uint8_t current = pio_read_8(ne2k->port + DP_CURR); … … 491 491 /* No more frames to process */ 492 492 break; 493 493 494 494 recv_header_t header; 495 495 size_t size = sizeof(header); 496 496 size_t offset = boundary * DP_PAGE; 497 497 498 498 /* Get the frame header */ 499 499 pio_write_8(ne2k->port + DP_RBCR0, size & 0xff); … … 502 502 pio_write_8(ne2k->port + DP_RSAR1, (offset >> 8) & 0xff); 503 503 pio_write_8(ne2k->port + DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA); 504 504 505 505 pio_read_buf_16(ne2k->data_port, (void *) &header, size); 506 506 … … 508 508 (((size_t) header.rbcl) | (((size_t) header.rbch) << 8)) - size; 509 509 uint8_t next = header.next; 510 510 511 511 if ((length < ETH_MIN_PACK_SIZE) 512 512 || (length > ETH_MAX_PACK_SIZE_TAGGED)) { … … 535 535 break; 536 536 } 537 537 538 538 /* 539 539 * Update the boundary pointer … … 585 585 ne2k->sq.dirty = false; 586 586 ne2k->sq.size = 0; 587 587 588 588 /* Signal a next frame to be sent */ 589 589 fibril_condvar_broadcast(&ne2k->sq_cv); … … 615 615 ne2k_reset(ne2k); 616 616 } 617 617 618 618 /* Unmask interrupts to be processed in the next round */ 619 619 pio_write_8(ne2k->port + DP_IMR, … … 627 627 else 628 628 ne2k->receive_configuration &= ~RCR_AB; 629 629 630 630 pio_write_8(ne2k->port + DP_RCR, ne2k->receive_configuration); 631 631 } … … 637 637 else 638 638 ne2k->receive_configuration &= ~RCR_AM; 639 639 640 640 pio_write_8(ne2k->port + DP_RCR, ne2k->receive_configuration); 641 641 } … … 647 647 else 648 648 ne2k->receive_configuration &= ~RCR_PRO; 649 649 650 650 pio_write_8(ne2k->port + DP_RCR, ne2k->receive_configuration); 651 651 } … … 655 655 /* Select Page 1 and stop all transfers */ 656 656 pio_write_8(ne2k->port + DP_CR, CR_PS_P1 | CR_DM_ABORT | CR_STP); 657 657 658 658 pio_write_8(ne2k->port + DP_MAR0, (uint8_t) hash); 659 659 pio_write_8(ne2k->port + DP_MAR1, (uint8_t) (hash >> 8)); … … 664 664 pio_write_8(ne2k->port + DP_MAR6, (uint8_t) (hash >> 48)); 665 665 pio_write_8(ne2k->port + DP_MAR7, (uint8_t) (hash >> 56)); 666 666 667 667 /* Select Page 0 and resume transfers */ 668 668 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_DM_ABORT | CR_STA);
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