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  • kernel/arch/arm32/include/regutils.h

    r9d58539 ra57b751  
    4141#define STATUS_REG_MODE_MASK         0x1f
    4242
    43 #define CP15_R1_HIGH_VECTORS_BIT     (1 << 13)
     43/* COntrol register bit values see ch. B4.1.130 of ARM Architecture Reference
     44 * Manual ARMv7-A and ARMv7-R edition, page 1687 */
     45#define CP15_R1_MMU_EN            (1 << 0)
     46#define CP15_R1_ALIGN_CHECK_EN    (1 << 1)  /* Allow alignemnt check */
     47#define CP15_R1_CACHE_EN          (1 << 2)
     48#define CP15_R1_CP15_BARRIER_EN   (1 << 5)
     49#define CP15_R1_B_EN              (1 << 7)  /* ARMv6- only big endian switch */
     50#define CP15_R1_SWAP_EN           (1 << 10)
     51#define CP15_R1_BRANCH_PREDICT_EN (1 << 11)
     52#define CP15_R1_INST_CACHE_EN     (1 << 12)
     53#define CP15_R1_HIGH_VECTORS_EN   (1 << 13)
     54#define CP15_R1_ROUND_ROBIN_EN    (1 << 14)
     55#define CP15_R1_HW_ACCESS_FLAG_EN (1 << 17)
     56#define CP15_R1_WRITE_XN_EN       (1 << 19) /* Only if virt. supported */
     57#define CP15_R1_USPCE_WRITE_XN_EN (1 << 20) /* Only if virt. supported */
     58#define CP15_R1_FAST_IRQ_EN       (1 << 21) /* Disbale impl.specific features */
     59#define CP15_R1_UNALIGNED_EN      (1 << 22) /* Must be 1 on armv7 */
     60#define CP15_R1_IRQ_VECTORS_EN    (1 << 24)
     61#define CP15_R1_BIG_ENDIAN_EXC    (1 << 25)
     62#define CP15_R1_NMFI_EN           (1 << 27)
     63#define CP15_R1_TEX_REMAP_EN      (1 << 28)
     64#define CP15_R1_ACCESS_FLAG_EN    (1 << 29)
     65#define CP15_R1_THUMB_EXC_EN      (1 << 30)
    4466
    4567/* ARM Processor Operation Modes */
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