Changes in uspace/drv/audio/hdaudio/hdactl.c [cf78637:a64970e1] in mainline

File:

• uspace/drv/audio/hdaudio/hdactl.c (modified) (3 diffs)

uspace/drv/audio/hdaudio/hdactl.c

@@ -1 +1 @@
 /*
- * Copyright (c) 2014 Jiri Svoboda
+ * Copyright (c) 2025 Jiri Svoboda
  * All rights reserved.
  *
@@ -628 +628 @@
 }
 
+void hda_ctl_quiesce(hda_ctl_t *ctl)
+{
+        uint32_t gctl;
+
+        ddf_msg(LVL_DEBUG, "hda_ctl_quiesce(): Resetting controller.");
+        gctl = hda_reg32_read(&ctl->hda->regs->gctl);
+        hda_reg32_write(&ctl->hda->regs->gctl,
+            gctl & ~BIT_V(uint32_t, gctl_crst));
+}
+
 errno_t hda_cmd(hda_t *hda, uint32_t verb, uint32_t *resp)
 {
@@ -670 +680 @@
 }
 
+static void hda_ctl_check_fifo_error(hda_ctl_t *ctl)
+{
+        int i;
+        uint8_t sts;
+
+        /*
+         * XXX Ideally the interrupt handler would tell us which stream
+         * has the error.
+         */
+
+        for (i = 0; i < 30; i++) {
+                sts = hda_reg8_read(&ctl->hda->regs->sdesc[i].sts);
+                if ((sts & BIT_V(uint8_t, sdsts_fifoe)) != 0 && (sts & 0x80) == 0) {
+                        ddf_msg(LVL_WARN, "sts[%d] = 0x%hhx\n", i, sts);
+                        hda_reg8_write(&ctl->hda->regs->sdesc[i].sts,
+                            BIT_V(uint8_t, sdsts_fifoe));
+                }
+        }
+}
+
 void hda_ctl_interrupt(hda_ctl_t *ctl)
 {
+        ddf_msg(LVL_DEBUG, "hda_ctl_interrupt");
+        hda_ctl_check_fifo_error(ctl);
         hda_ctl_process_rirb(ctl);
 }