Changeset a7f7b9c3 in mainline

Timestamp:

2021-08-08T17:47:47Z (3 years ago)

Author:

jxsvoboda <5887334+jxsvoboda@…>

Branches:

master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

2177b39

Parents:

3e6bca8

git-author:

Maurizio Lombardi <mlombard@…> (2021-08-06 07:56:17)

git-committer:

jxsvoboda <5887334+jxsvoboda@…> (2021-08-08 17:47:47)

Message:

arm32: performance boost on raspberry pi

• enable the icache and branch prediction for ARMv6
• flush the branch predictor after writing to the TTBR0 register

Signed-off-by: Maurizio Lombardi <mlombard@…>

Location:

kernel/arch/arm32

Files:

• include/arch/mm/page.h (modified) (1 diff)
• src/cpu/cpu.c (modified) (1 diff)

kernel/arch/arm32/include/arch/mm/page.h

@@ -159 +159 @@
 #endif
         TTBR0_write(val);
+#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
+        BPIALL_write(0);
+#endif
 }
 

kernel/arch/arm32/src/cpu/cpu.c

@@ -170 +170 @@
          */
         control_reg |= SCTLR_CACHE_EN_FLAG;
-#endif
-#ifdef PROCESSOR_ARCH_armv7_a
         /*
          * ICache coherency is elaborated on in barrier.h.