Changes in kernel/arch/arm32/src/exception.c [9a5ccc14:a99a3d7] in mainline

File:

• kernel/arch/arm32/src/exception.c (modified) (6 diffs)

kernel/arch/arm32/src/exception.c

@@ -39 +39 @@
 #include <interrupt.h>
 #include <arch/mm/page_fault.h>
-#include <arch/cp15.h>
 #include <arch/barrier.h>
 #include <print.h>
@@ -74 +73 @@
         /* make it LDR instruction and store at exception vector */
         *vector = handler_address_ptr | LDR_OPCODE;
-        smc_coherence(vector);
+        smc_coherence(*vector);
         
         /* store handler's address */
@@ -118 +117 @@
 
 #ifdef HIGH_EXCEPTION_VECTORS
-/** Activates use of high exception vectors addresses.
- *
- * "High vectors were introduced into some implementations of ARMv4 and are
- * required in ARMv6 implementations. High vectors allow the exception vector
- * locations to be moved from their normal address range 0x00000000-0x0000001C
- * at the bottom of the 32-bit address space, to an alternative address range
- * 0xFFFF0000-0xFFFF001C near the top of the address space. These alternative
- * locations are known as the high vectors.
- *
- * Prior to ARMv6, it is IMPLEMENTATION DEFINED whether the high vectors are
- * supported. When they are, a hardware configuration input selects whether
- * the normal vectors or the high vectors are to be used from
- * reset." ARM Architecture Reference Manual A2.6.11 (p. 64 in the PDF).
- *
- * ARM920T (gta02) TRM A2.3.5 (PDF p. 36) and ARM926EJ-S (icp) 2.3.2 (PDF p. 42)
- * say that armv4 an armv5 chips that we support implement this.
- */
+/** Activates use of high exception vectors addresses. */
 static void high_vectors(void)
 {
-        uint32_t control_reg = SCTLR_read();
+        uint32_t control_reg;
+        
+        asm volatile (
+                "mrc p15, 0, %[control_reg], c1, c1"
+                : [control_reg] "=r" (control_reg)
+        );
         
         /* switch on the high vectors bit */
-        control_reg |= SCTLR_HIGH_VECTORS_EN_FLAG;
+        control_reg |= CP15_R1_HIGH_VECTORS_BIT;
         
-        SCTLR_write(control_reg);
+        asm volatile (
+                "mcr p15, 0, %[control_reg], c1, c1"
+                :: [control_reg] "r" (control_reg)
+        );
 }
 #endif
@@ -155 +146 @@
 }
 
-/** Undefined instruction exception handler.
- *
- * Calls scheduler_fpu_lazy_request
- */
-static void undef_insn_exception(unsigned int exc_no, istate_t *istate)
-{
-#ifdef CONFIG_FPU
-        if (handle_if_fpu_exception()) {
-                /*
-                 * Retry the failing instruction,
-                 * ARM Architecture Reference Manual says on p.B1-1169
-                 * that offset for undef instruction exception is 4
-                 */
-                istate->pc -= 4;
-                return;
-        }
-#endif
-        fault_if_from_uspace(istate, "Undefined instruction.");
-        panic_badtrap(istate, exc_no, "Undefined instruction.");
-}
-
 /** Initializes exception handling.
  *
@@ -183 +153 @@
 void exception_init(void)
 {
-        // TODO check for availability of high vectors for <= armv5
 #ifdef HIGH_EXCEPTION_VECTORS
         high_vectors();
@@ -189 +158 @@
         install_exception_handlers();
         
-        exc_register(EXC_UNDEF_INSTR, "undefined instruction", true,
-            (iroutine_t) undef_insn_exception);
         exc_register(EXC_IRQ, "interrupt", true,
             (iroutine_t) irq_exception);