Changeset a9ac978 in mainline
- Timestamp:
- 2006-09-27T20:11:34Z (18 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 00b38a3
- Parents:
- 86b31ba9
- Files:
-
- 2 added
- 14 edited
Legend:
- Unmodified
- Added
- Removed
-
boot/arch/sparc64/loader/ofwarch.c
r86b31ba9 ra9ac978 36 36 #include <printf.h> 37 37 #include <string.h> 38 #include <register.h> 38 39 #include "main.h" 39 40 … … 54 55 } 55 56 56 57 #define ASI_UPA_CONFIG 0x4a58 #define UPA_CONFIG_MID_SHIFT 1759 #define UPA_CONFIG_MID_MASK 0x1f60 61 57 int ofw_cpu(void) 62 58 { … … 75 71 current_mid >>= UPA_CONFIG_MID_SHIFT; 76 72 current_mid &= UPA_CONFIG_MID_MASK; 73 74 int cpus; 77 75 78 for ( ; node != 0 && node != -1; node = ofw_get_peer_node(node)) {76 for (cpus = 0; node != 0 && node != -1; node = ofw_get_peer_node(node), cpus++) { 79 77 if (ofw_get_property(node, "device_type", type_name, sizeof(type_name)) > 0) { 80 78 if (strcmp(type_name, "cpu") == 0) { … … 94 92 } 95 93 96 return 1;94 return cpus; 97 95 } -
boot/arch/sparc64/loader/register.h
r86b31ba9 ra9ac978 33 33 #define PSTATE_AM_BIT 8 34 34 35 #define ASI_UPA_CONFIG 0x4a 36 #define UPA_CONFIG_MID_SHIFT 17 37 #define UPA_CONFIG_MID_MASK 0x1f 38 35 39 #endif -
kernel/arch/sparc64/Makefile.inc
r86b31ba9 ra9ac978 71 71 CONFIG_OFW_TREE = y 72 72 73 ifeq ($(CONFIG_SMP),y) 74 DEFS += -DCONFIG_SMP 75 endif 76 73 77 ARCH_SOURCES = \ 74 78 arch/$(ARCH)/src/cpu/cpu.c \ … … 99 103 arch/$(ARCH)/src/drivers/scr.c 100 104 105 ifeq ($(CONFIG_SMP),y) 106 ARCH_SOURCES += \ 107 arch/$(ARCH)/src/smp/ipi.c \ 108 arch/$(ARCH)/src/smp/smp.c 109 endif 110 101 111 ifeq ($(CONFIG_TSB),y) 102 112 ARCH_SOURCES += \ -
kernel/arch/sparc64/include/atomic.h
r86b31ba9 ra9ac978 97 97 { 98 98 uint64_t v = 1; 99 volatile uintptr_t x = (uint64_t) &val->count; 99 100 100 __asm__ volatile ("casx %0, %2, %1\n" : "+m" (* val), "+r" (v) : "r" (0));101 __asm__ volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *) x)), "+r" (v) : "r" (0)); 101 102 102 103 return v; … … 107 108 uint64_t tmp1 = 1; 108 109 uint64_t tmp2; 110 111 volatile uintptr_t x = (uint64_t) &val->count; 109 112 110 113 __asm__ volatile ( … … 120 123 "nop\n" 121 124 "2:\n" 122 : "+m" (* val), "+r" (tmp1), "+r" (tmp2) : "r" (0)125 : "+m" (*((uint64_t *) x)), "+r" (tmp1), "+r" (tmp2) : "r" (0) 123 126 ); 124 127 -
kernel/arch/sparc64/include/cpu.h
r86b31ba9 ra9ac978 36 36 #define KERN_sparc64_CPU_H_ 37 37 38 #include <arch/types.h> 38 39 #include <arch/register.h> 39 40 … … 52 53 53 54 struct cpu_arch { 55 uint32_t mid; /**< Processor ID as read from UPA_CONFIG. */ 54 56 ver_reg_t ver; 55 uint32_t clock_frequency; 57 uint32_t clock_frequency; /**< Processor frequency in MHz. */ 56 58 }; 57 59 -
kernel/arch/sparc64/include/interrupt.h
r86b31ba9 ra9ac978 41 41 #include <arch/regdef.h> 42 42 43 #define IRQ_COUNT 1 /* TODO */43 #define IRQ_COUNT 1 /* TODO */ 44 44 45 45 #define IVT_ITEMS 15 46 46 #define IVT_FIRST 1 47 48 #define VECTOR_TLB_SHOOTDOWN_IPI 0 /* TODO */ 47 49 48 50 struct istate { -
kernel/arch/sparc64/include/regdef.h
r86b31ba9 ra9ac978 56 56 #define WSTATE_OTHER(n) ((n)<<3) 57 57 58 #define UPA_CONFIG_MID_SHIFT 17 59 #define UPA_CONFIG_MID_MASK 0x1f 60 58 61 #endif 59 62 -
kernel/arch/sparc64/src/cpu/cpu.c
r86b31ba9 ra9ac978 51 51 52 52 upa_config.value = upa_config_read(); 53 CPU->arch.mid = upa_config.mid; 54 53 55 node = ofw_tree_find_child_by_device_type(ofw_tree_lookup("/"), "cpu"); 54 56 while (node) { … … 58 60 if (prop && prop->value) { 59 61 mid = *((uint32_t *) prop->value); 60 if (mid == upa_config.mid) {62 if (mid == CPU->arch.mid) { 61 63 prop = ofw_tree_getprop(node, "clock-frequency"); 62 64 if (prop && prop->value) … … 79 81 /** Print version information for a processor. 80 82 * 83 * This function is called by the bootstrap processor. 84 * 81 85 * @param m Processor structure of the CPU for which version information is to be printed. 82 86 */ … … 85 89 char *manuf, *impl; 86 90 87 switch ( CPU->arch.ver.manuf) {88 91 switch (m->arch.ver.manuf) { 92 case MANUF_FUJITSU: 89 93 manuf = "Fujitsu"; 90 94 break; 91 95 case MANUF_ULTRASPARC: 92 96 manuf = "UltraSPARC"; 93 97 break; 94 98 case MANUF_SUN: 95 99 manuf = "Sun"; 96 100 break; 97 101 default: 98 102 manuf = "Unknown"; 99 103 break; … … 101 105 102 106 switch (CPU->arch.ver.impl) { 103 107 case IMPL_ULTRASPARCI: 104 108 impl = "UltraSPARC I"; 105 109 break; 106 110 case IMPL_ULTRASPARCII: 107 111 impl = "UltraSPARC II"; 108 112 break; 109 113 case IMPL_ULTRASPARCII_I: 110 114 impl = "UltraSPARC IIi"; 111 115 break; 112 116 case IMPL_ULTRASPARCII_E: 113 117 impl = "UltraSPARC IIe"; 114 118 break; 115 119 case IMPL_ULTRASPARCIII: 116 120 impl = "UltraSPARC III"; 117 121 break; 118 122 case IMPL_ULTRASPARCIV_PLUS: 119 123 impl = "UltraSPARC IV+"; 120 124 break; 121 125 case IMPL_SPARC64V: 122 126 impl = "SPARC 64V"; 123 127 break; 124 128 default: 125 129 impl = "Unknown"; 126 130 break; … … 128 132 129 133 printf("cpu%d: manuf=%s, impl=%s, mask=%d (%dMHz)\n", 130 CPU->id, manuf, impl, CPU->arch.ver.mask, CPU->arch.clock_frequency/1000000);134 m->id, manuf, impl, m->arch.ver.mask, m->arch.clock_frequency/1000000); 131 135 } 132 136 -
kernel/arch/sparc64/src/mm/as.c
r86b31ba9 ra9ac978 38 38 #include <genarch/mm/asid_fifo.h> 39 39 #include <debug.h> 40 #include <config.h> 40 41 41 42 #ifdef CONFIG_TSB … … 52 53 void as_arch_init(void) 53 54 { 54 as_operations = &as_ht_operations; 55 asid_fifo_init(); 55 if (config.cpu_active == 1) { 56 as_operations = &as_ht_operations; 57 asid_fifo_init(); 58 } 56 59 } 57 60 -
kernel/arch/sparc64/src/mm/frame.c
r86b31ba9 ra9ac978 54 54 pfn_t confdata; 55 55 56 for (i = 0; i < bootinfo.memmap.count; i++) { 57 uintptr_t start = bootinfo.memmap.zones[i].start; 58 size_t size = bootinfo.memmap.zones[i].size; 56 if (config.cpu_active == 1) { 57 for (i = 0; i < bootinfo.memmap.count; i++) { 58 uintptr_t start = bootinfo.memmap.zones[i].start; 59 size_t size = bootinfo.memmap.zones[i].size; 59 60 60 /*61 * The memmap is created by HelenOS boot loader.62 * It already contains no holes.63 */61 /* 62 * The memmap is created by HelenOS boot loader. 63 * It already contains no holes. 64 */ 64 65 65 confdata = ADDR2PFN(start);66 if (confdata == 0)67 confdata = 2;68 zone_create(ADDR2PFN(start), SIZE2FRAMES(ALIGN_DOWN(size, FRAME_SIZE)), confdata, 0);66 confdata = ADDR2PFN(start); 67 if (confdata == 0) 68 confdata = 2; 69 zone_create(ADDR2PFN(start), SIZE2FRAMES(ALIGN_DOWN(size, FRAME_SIZE)), confdata, 0); 69 70 70 last_frame = max(last_frame, start + ALIGN_UP(size, FRAME_SIZE)); 71 last_frame = max(last_frame, start + ALIGN_UP(size, FRAME_SIZE)); 72 } 71 73 } 72 74 -
kernel/arch/sparc64/src/mm/page.c
r86b31ba9 ra9ac978 41 41 #include <debug.h> 42 42 #include <align.h> 43 #include <config.h> 43 44 45 #ifdef CONFIG_SMP 46 /** Entries locked in DTLB of BSP. 47 * 48 * Application processors need to have the same locked entries 49 * in their DTLBs as the bootstrap processor. 50 */ 51 static struct { 52 uintptr_t virt_page; 53 uintptr_t phys_page; 54 int pagesize_code; 55 } bsp_locked_dtlb_entry[DTLB_ENTRY_COUNT]; 56 57 /** Number of entries in bsp_locked_dtlb_entry array. */ 58 static count_t bsp_locked_dtlb_entries = 0; 59 #endif /* CONFIG_SMP */ 60 61 /** Perform sparc64 specific initialization of paging. */ 44 62 void page_arch_init(void) 45 63 { 46 page_mapping_operations = &ht_mapping_operations; 64 if (config.cpu_active == 1) { 65 page_mapping_operations = &ht_mapping_operations; 66 } else { 67 68 #ifdef CONFIG_SMP 69 int i; 70 71 /* 72 * Copy locked DTLB entries from the BSP. 73 */ 74 for (i = 0; i < bsp_locked_dtlb_entries; i++) { 75 dtlb_insert_mapping(bsp_locked_dtlb_entry[i].virt_page, 76 bsp_locked_dtlb_entry[i].phys_page, bsp_locked_dtlb_entry[i].pagesize_code, 77 true, false); 78 } 79 #endif 80 81 } 47 82 } 48 83 … … 68 103 int i; 69 104 105 ASSERT(config.cpu_active == 1); 106 70 107 struct { 71 int pagesize ;108 int pagesize_code; 72 109 size_t increment; 73 110 count_t count; … … 102 139 last_frame = ALIGN_UP(virtaddr + size, 1<<(order + FRAME_WIDTH)); 103 140 104 for (i = 0; i < sizemap[order].count; i++) 141 for (i = 0; i < sizemap[order].count; i++) { 142 /* 143 * First, insert the mapping into DTLB. 144 */ 105 145 dtlb_insert_mapping(virtaddr + i*sizemap[order].increment, 106 146 physaddr + i*sizemap[order].increment, 107 sizemap[order].pagesize, true, false); 147 sizemap[order].pagesize_code, true, false); 148 149 #ifdef CONFIG_SMP 150 /* 151 * Second, save the information about the mapping for APs. 152 */ 153 bsp_locked_dtlb_entry[bsp_locked_dtlb_entries].virt_page = virtaddr + i*sizemap[order].increment; 154 bsp_locked_dtlb_entry[bsp_locked_dtlb_entries].phys_page = physaddr + i*sizemap[order].increment; 155 bsp_locked_dtlb_entry[bsp_locked_dtlb_entries].pagesize_code = sizemap[order].pagesize_code; 156 bsp_locked_dtlb_entries++; 157 #endif 158 } 108 159 109 160 return virtaddr; -
kernel/arch/sparc64/src/sparc64.c
r86b31ba9 ra9ac978 71 71 void arch_pre_mm_init(void) 72 72 { 73 trap_init(); 73 if (config.cpu_active == 1) 74 trap_init(); 74 75 } 75 76 76 77 void arch_post_mm_init(void) 77 78 { 78 standalone_sparc64_console_init(); 79 if (config.cpu_active == 1) 80 standalone_sparc64_console_init(); 79 81 } 80 82 … … 91 93 thread_t *t; 92 94 93 /* 94 * Create thread that polls keyboard. 95 */ 96 t = thread_create(kkbdpoll, NULL, TASK, 0, "kkbdpoll"); 97 if (!t) 98 panic("cannot create kkbdpoll\n"); 99 thread_ready(t); 95 if (config.cpu_active == 1) { 96 /* 97 * Create thread that polls keyboard. 98 */ 99 t = thread_create(kkbdpoll, NULL, TASK, 0, "kkbdpoll"); 100 if (!t) 101 panic("cannot create kkbdpoll\n"); 102 thread_ready(t); 103 } 100 104 } 101 105 -
kernel/arch/sparc64/src/start.S
r86b31ba9 ra9ac978 27 27 # 28 28 29 #include <arch/arch.h> 29 30 #include <arch/regdef.h> 30 31 #include <arch/boot/boot.h> … … 33 34 #include <arch/mm/tlb.h> 34 35 #include <arch/mm/tte.h> 36 37 #ifdef CONFIG_SMP 38 #include <arch/context_offset.h> 39 #endif 35 40 36 41 .register %g2, #scratch … … 227 232 wrpr %g0, 0, %tl 228 233 229 brz %l7, 2f ! skip if you are not the bootstrap CPU 234 brz %l7, 1f ! skip if you are not the bootstrap CPU 235 nop 230 236 231 237 call arch_pre_main … … 237 243 /* Not reached. */ 238 244 245 0: 246 ba 0b 247 nop 248 249 250 /* 251 * Read MID from the processor. 252 */ 253 1: 254 ldxa [%g0] ASI_UPA_CONFIG, %g1 255 srlx %g1, UPA_CONFIG_MID_SHIFT, %g1 256 and %g1, UPA_CONFIG_MID_MASK, %g1 257 258 /* 259 * Active loop for APs until the BSP picks them up. 260 * A processor cannot leave the loop until the 261 * global variable 'waking_up_mid' equals its 262 * MID. 263 */ 264 set waking_up_mid, %g2 239 265 2: 240 b 2b 241 nop 266 ldx [%g2], %g3 267 cmp %g3, %g1 268 bne 2b 269 nop 270 271 #ifdef CONFIG_SMP 272 /* 273 * Configure stack for the AP. 274 * The AP is expected to use the stack saved 275 * in the ctx global variable. 276 */ 277 set ctx, %g1 278 add %g1, OFFSET_SP, %g1 279 ldx [%g1], %o6 280 281 call main_ap 282 nop 283 #endif 284 285 /* Not reached. */ 286 287 0: 288 ba 0b 289 nop -
kernel/kernel.config
r86b31ba9 ra9ac978 72 72 73 73 # Support for SMP 74 ! [ARCH=ia32|ARCH=amd64|ARCH=xen32 ] CONFIG_SMP (y/n)74 ! [ARCH=ia32|ARCH=amd64|ARCH=xen32|ARCH=sparc64] CONFIG_SMP (y/n) 75 75 76 76 # Improved support for hyperthreading
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