Changes in / [721d4e85:aa30c7f] in mainline


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Files:
2 deleted
24 edited

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  • defaults/sparc64/sun4v/Makefile.config

    r721d4e85 raa30c7f  
    1111CONFIG_SMP = n
    1212
     13CONFIG_TSB = n
     14
    1315CONFIG_FB = n
    1416

  • kernel/arch/sparc64/Makefile.inc

    r721d4e85 raa30c7f  
    7575        arch/$(KARCH)/src/dummy.s \
    7676        arch/$(KARCH)/src/mm/$(USARCH)/as.c \
     77        arch/$(KARCH)/src/mm/cache.S \
    7778        arch/$(KARCH)/src/mm/$(USARCH)/frame.c \
    7879        arch/$(KARCH)/src/mm/page.c \
    … …  
    9394        arch/$(KARCH)/src/drivers/pci.c \
    9495        arch/$(KARCH)/src/drivers/fhc.c
    95 
    96 ifeq ($(USARCH),sun4u)
    97         ARCH_SOURCES += \
    98                 arch/$(KARCH)/src/mm/cache.S
    99 endif
    10096
    10197ifeq ($(USARCH),sun4v)

  • kernel/arch/sparc64/include/mm/as.h

    r721d4e85 raa30c7f  
    3636#define KERN_sparc64_AS_H_
    3737
    38 #if defined (SUN4U)
    39 #include <arch/mm/sun4u/as.h>
    40 #elif defined (SUN4V)
    41 #include <arch/mm/sun4v/as.h>
     38#include <arch/mm/tte.h>
     39
     40#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH      1
     41
     42#define KERNEL_ADDRESS_SPACE_START_ARCH         (unsigned long) 0x0000000000000000
     43#define KERNEL_ADDRESS_SPACE_END_ARCH           (unsigned long) 0xffffffffffffffff
     44#define USER_ADDRESS_SPACE_START_ARCH           (unsigned long) 0x0000000000000000
     45#define USER_ADDRESS_SPACE_END_ARCH             (unsigned long) 0xffffffffffffffff
     46
     47#define USTACK_ADDRESS_ARCH     (0xffffffffffffffffULL - (PAGE_SIZE - 1))
     48
     49#ifdef CONFIG_TSB
     50
     51/** TSB Tag Target register. */
     52typedef union tsb_tag_target {
     53        uint64_t value;
     54        struct {
     55                unsigned invalid : 1;   /**< Invalidated by software. */
     56                unsigned : 2;
     57                unsigned context : 13;  /**< Software ASID. */
     58                unsigned : 6;
     59                uint64_t va_tag : 42;   /**< Virtual address bits <63:22>. */
     60        } __attribute__ ((packed));
     61} tsb_tag_target_t;
     62
     63/** TSB entry. */
     64typedef struct tsb_entry {
     65        tsb_tag_target_t tag;
     66        tte_data_t data;
     67} __attribute__ ((packed)) tsb_entry_t;
     68
     69typedef struct {
     70        tsb_entry_t *itsb;
     71        tsb_entry_t *dtsb;
     72} as_arch_t;
     73
     74#else
     75
     76typedef struct {
     77} as_arch_t;
     78
     79#endif /* CONFIG_TSB */
     80
     81#include <genarch/mm/as_ht.h>
     82
     83#ifdef CONFIG_TSB
     84#include <arch/mm/tsb.h>
     85#define as_invalidate_translation_cache(as, page, cnt) \
     86        tsb_invalidate((as), (page), (cnt))
     87#else
     88#define as_invalidate_translation_cache(as, page, cnt)
    4289#endif
     90
     91extern void as_arch_init(void);
    4392
    4493#endif

  • kernel/arch/sparc64/include/mm/sun4u/tlb.h

    r721d4e85 raa30c7f  
    684684
    685685extern void dump_sfsr_and_sfar(void);
    686 extern void describe_dmmu_fault(void);
    687686
    688687#endif /* !def __ASM__ */

  • kernel/arch/sparc64/include/mm/sun4v/frame.h

    r721d4e85 raa30c7f  
    3333 */
    3434
    35 #ifndef KERN_sparc64_sun4v_FRAME_H_
    36 #define KERN_sparc64_sun4v_FRAME_H_
     35#ifndef KERN_sparc64_SUN4V_FRAME_H_
     36#define KERN_sparc64_SUN4V_FRAME_H_
    3737
     38/*
     39 * Page size supported by the MMU.
     40 * For 8K there is the nasty illegal virtual aliasing problem.
     41 * Therefore, the kernel uses 8K only internally on the TLB and TSB levels.
     42 */
    3843#define MMU_FRAME_WIDTH         13      /* 8K */
    3944#define MMU_FRAME_SIZE          (1 << MMU_FRAME_WIDTH)
    … …  
    4752#include <arch/types.h>
    4853
     54union frame_address {
     55        uintptr_t address;
     56        struct {
     57#if defined (US)
     58                unsigned : 23;
     59                uint64_t pfn : 28;              /**< Physical Frame Number. */
     60#elif defined (US3)
     61                unsigned : 21;
     62                uint64_t pfn : 30;              /**< Physical Frame Number. */
     63#endif
     64                unsigned offset : 13;           /**< Offset. */
     65        } __attribute__ ((packed));
     66};
     67
     68typedef union frame_address frame_address_t;
     69
    4970extern uintptr_t last_frame;
     71//MH
     72//extern uintptr_t end_of_identity;
     73
    5074extern void frame_arch_init(void);
    5175#define physmem_print()

  • kernel/arch/sparc64/include/mm/sun4v/mmu.h

    r721d4e85 raa30c7f  
    4545#define ASI_SECONDARY_CONTEXT_REG       0x21    /**< secondary context register ASI. */
    4646
     47
     48
     49
     50
     51
     52
     53
     54
     55
     56
     57/* I-MMU ASIs. */
     58#define ASI_IMMU                        0x50
     59#define ASI_IMMU_TSB_8KB_PTR_REG        0x51   
     60#define ASI_IMMU_TSB_64KB_PTR_REG       0x52
     61#define ASI_ITLB_DATA_IN_REG            0x54
     62#define ASI_ITLB_DATA_ACCESS_REG        0x55
     63#define ASI_ITLB_TAG_READ_REG           0x56
     64#define ASI_IMMU_DEMAP                  0x57
     65
     66/* Virtual Addresses within ASI_IMMU. */
     67#define VA_IMMU_TSB_TAG_TARGET          0x0     /**< IMMU TSB tag target register. */
     68#define VA_IMMU_SFSR                    0x18    /**< IMMU sync fault status register. */
     69#define VA_IMMU_TSB_BASE                0x28    /**< IMMU TSB base register. */
     70#define VA_IMMU_TAG_ACCESS              0x30    /**< IMMU TLB tag access register. */
     71#if defined (US3)
     72#define VA_IMMU_PRIMARY_EXTENSION       0x48    /**< IMMU TSB primary extension register */
     73#define VA_IMMU_NUCLEUS_EXTENSION       0x58    /**< IMMU TSB nucleus extension register */
     74#endif
     75
     76
     77/* D-MMU ASIs. */
     78#define ASI_DMMU                        0x58
     79#define ASI_DMMU_TSB_8KB_PTR_REG        0x59   
     80#define ASI_DMMU_TSB_64KB_PTR_REG       0x5a
     81#define ASI_DMMU_TSB_DIRECT_PTR_REG     0x5b
     82#define ASI_DTLB_DATA_IN_REG            0x5c
     83#define ASI_DTLB_DATA_ACCESS_REG        0x5d
     84#define ASI_DTLB_TAG_READ_REG           0x5e
     85#define ASI_DMMU_DEMAP                  0x5f
     86
     87/* Virtual Addresses within ASI_DMMU. */
     88#define VA_DMMU_TSB_TAG_TARGET          0x0     /**< DMMU TSB tag target register. */
     89#define VA_PRIMARY_CONTEXT_REG          0x8     /**< DMMU primary context register. */
     90#define VA_SECONDARY_CONTEXT_REG        0x10    /**< DMMU secondary context register. */
     91#define VA_DMMU_SFSR                    0x18    /**< DMMU sync fault status register. */
     92#define VA_DMMU_SFAR                    0x20    /**< DMMU sync fault address register. */
     93#define VA_DMMU_TSB_BASE                0x28    /**< DMMU TSB base register. */
     94#define VA_DMMU_TAG_ACCESS              0x30    /**< DMMU TLB tag access register. */
     95#define VA_DMMU_VA_WATCHPOINT_REG       0x38    /**< DMMU VA data watchpoint register. */
     96#define VA_DMMU_PA_WATCHPOINT_REG       0x40    /**< DMMU PA data watchpoint register. */
     97#if defined (US3)
     98#define VA_DMMU_PRIMARY_EXTENSION       0x48    /**< DMMU TSB primary extension register */
     99#define VA_DMMU_SECONDARY_EXTENSION     0x50    /**< DMMU TSB secondary extension register */
     100#define VA_DMMU_NUCLEUS_EXTENSION       0x58    /**< DMMU TSB nucleus extension register */
     101#endif
     102
     103#ifndef __ASM__
     104
     105#include <arch/asm.h>
     106#include <arch/barrier.h>
     107#include <arch/types.h>
     108
     109#if defined(US)
     110/** LSU Control Register. */
     111typedef union {
     112        uint64_t value;
     113        struct {
     114                unsigned : 23;
     115                unsigned pm : 8;
     116                unsigned vm : 8;
     117                unsigned pr : 1;
     118                unsigned pw : 1;
     119                unsigned vr : 1;
     120                unsigned vw : 1;
     121                unsigned : 1;
     122                unsigned fm : 16;       
     123                unsigned dm : 1;        /**< D-MMU enable. */
     124                unsigned im : 1;        /**< I-MMU enable. */
     125                unsigned dc : 1;        /**< D-Cache enable. */
     126                unsigned ic : 1;        /**< I-Cache enable. */
     127               
     128        } __attribute__ ((packed));
     129} lsu_cr_reg_t;
     130#endif /* US */
     131
     132#endif /* !def __ASM__ */
     133
     134
     135
     136
     137
     138
     139
     140
     141
     142
     143
     144
     145
     146
     147
     148
    47149#endif
    48150

  • kernel/arch/sparc64/include/mm/sun4v/tsb.h

    r721d4e85 raa30c7f  
    7171struct pte;
    7272
    73 extern void tsb_invalidate(struct as *as, uintptr_t page, uint64_t pages);
     73extern void tsb_invalidate(struct as *as, uintptr_t page, count_t pages);
    7474extern void itsb_pte_copy(struct pte *t);
    7575extern void dtsb_pte_copy(struct pte *t, bool ro);

  • kernel/arch/sparc64/include/mm/tlb.h

    r721d4e85 raa30c7f  
    3636#define KERN_sparc64_TLB_H_
    3737
    38 
    3938#if defined (SUN4U)
    4039#include <arch/mm/sun4u/tlb.h>

  • kernel/arch/sparc64/include/mm/tsb.h

    r721d4e85 raa30c7f  
    3636#define KERN_sparc64_TSB_H_
    3737
    38 #if defined (SUN4U)
    39 #include <arch/mm/sun4u/tsb.h>
    40 #elif defined (SUN4V)
    41 #include <arch/mm/sun4v/tsb.h>
     38/*
     39 * ITSB abd DTSB will claim 64K of memory, which
     40 * is a nice number considered that it is one of
     41 * the page sizes supported by hardware, which,
     42 * again, is nice because TSBs need to be locked
     43 * in TLBs - only one TLB entry will do.
     44 */
     45#define TSB_SIZE                        2       /* when changing this, change
     46                                                 * as.c as well */
     47#define ITSB_ENTRY_COUNT                (512 * (1 << TSB_SIZE))
     48#define DTSB_ENTRY_COUNT                (512 * (1 << TSB_SIZE))
     49
     50#define TSB_TAG_TARGET_CONTEXT_SHIFT    48
     51
     52#ifndef __ASM__
     53
     54#include <arch/mm/tte.h>
     55#include <arch/mm/mmu.h>
     56#include <arch/types.h>
     57
     58/** TSB Base register. */
     59typedef union tsb_base_reg {
     60        uint64_t value;
     61        struct {
     62                uint64_t base : 51;     /**< TSB base address, bits 63:13. */
     63                unsigned split : 1;     /**< Split vs. common TSB for 8K and 64K
     64                                         * pages. HelenOS uses only 8K pages
     65                                         * for user mappings, so we always set
     66                                         * this to 0.
     67                                         */
     68                unsigned : 9;
     69                unsigned size : 3;      /**< TSB size. Number of entries is
     70                                         * 512 * 2^size. */
     71        } __attribute__ ((packed));
     72} tsb_base_reg_t;
     73
     74/** Read ITSB Base register.
     75 *
     76 * @return Content of the ITSB Base register.
     77 */
     78static inline uint64_t itsb_base_read(void)
     79{
     80        return asi_u64_read(ASI_IMMU, VA_IMMU_TSB_BASE);
     81}
     82
     83/** Read DTSB Base register.
     84 *
     85 * @return Content of the DTSB Base register.
     86 */
     87static inline uint64_t dtsb_base_read(void)
     88{
     89        return asi_u64_read(ASI_DMMU, VA_DMMU_TSB_BASE);
     90}
     91
     92/** Write ITSB Base register.
     93 *
     94 * @param v New content of the ITSB Base register.
     95 */
     96static inline void itsb_base_write(uint64_t v)
     97{
     98        asi_u64_write(ASI_IMMU, VA_IMMU_TSB_BASE, v);
     99}
     100
     101/** Write DTSB Base register.
     102 *
     103 * @param v New content of the DTSB Base register.
     104 */
     105static inline void dtsb_base_write(uint64_t v)
     106{
     107        asi_u64_write(ASI_DMMU, VA_DMMU_TSB_BASE, v);
     108}
     109
     110#if defined (US3)
     111
     112/** Write DTSB Primary Extension register.
     113 *
     114 * @param v New content of the DTSB Primary Extension register.
     115 */
     116static inline void dtsb_primary_extension_write(uint64_t v)
     117{
     118        asi_u64_write(ASI_DMMU, VA_DMMU_PRIMARY_EXTENSION, v);
     119}
     120
     121/** Write DTSB Secondary Extension register.
     122 *
     123 * @param v New content of the DTSB Secondary Extension register.
     124 */
     125static inline void dtsb_secondary_extension_write(uint64_t v)
     126{
     127        asi_u64_write(ASI_DMMU, VA_DMMU_SECONDARY_EXTENSION, v);
     128}
     129
     130/** Write DTSB Nucleus Extension register.
     131 *
     132 * @param v New content of the DTSB Nucleus Extension register.
     133 */
     134static inline void dtsb_nucleus_extension_write(uint64_t v)
     135{
     136        asi_u64_write(ASI_DMMU, VA_DMMU_NUCLEUS_EXTENSION, v);
     137}
     138
     139/** Write ITSB Primary Extension register.
     140 *
     141 * @param v New content of the ITSB Primary Extension register.
     142 */
     143static inline void itsb_primary_extension_write(uint64_t v)
     144{
     145        asi_u64_write(ASI_IMMU, VA_IMMU_PRIMARY_EXTENSION, v);
     146}
     147
     148/** Write ITSB Nucleus Extension register.
     149 *
     150 * @param v New content of the ITSB Nucleus Extension register.
     151 */
     152static inline void itsb_nucleus_extension_write(uint64_t v)
     153{
     154        asi_u64_write(ASI_IMMU, VA_IMMU_NUCLEUS_EXTENSION, v);
     155}
     156
    42157#endif
     158
     159/* Forward declarations. */
     160struct as;
     161struct pte;
     162
     163extern void tsb_invalidate(struct as *as, uintptr_t page, size_t pages);
     164extern void itsb_pte_copy(struct pte *t, size_t index);
     165extern void dtsb_pte_copy(struct pte *t, size_t index, bool ro);
     166
     167#endif /* !def __ASM__ */
    43168
    44169#endif

  • kernel/arch/sparc64/include/sun4v/arch.h

    r721d4e85 raa30c7f  
    5858#define SCRATCHPAD_WBUF         0x18
    5959
     60//MH - remove when cpu.h is forked
     61#define ASI_NUCLEUS_QUAD_LDD    0x24    /** ASI for 16-byte atomic loads. */
     62#define ASI_DCACHE_TAG          0x47    /** ASI D-Cache Tag. */
     63#define ASI_ICBUS_CONFIG        0x4a    /** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */
     64
    6065#endif
    6166

  • kernel/arch/sparc64/include/sun4v/hypercall.h

    r721d4e85 raa30c7f  
    8181#define EBADPGSZ        4       /**< Invalid pagesize encoding */
    8282#define EBADTSB         5       /**< Invalid TSB description */
    83 #define HV_EINVAL       6       /**< Invalid argument */
     83#define EINVAL          6       /**< Invalid argument */
    8484#define EBADTRAP        7       /**< Invalid function number */
    8585#define EBADALIGN       8       /**< Invalid address alignment */
    … …  
    9292#define ETOOMANY        15      /**< Too many items specified / limit reached */
    9393#define ECHANNEL        16      /**< Invalid LDC channel */
    94 #define HV_EBUSY        17      /**< Operation failed as resource is otherwise busy */
     94#define EBUSY           17      /**< Operation failed as resource is otherwise busy */
    9595
    9696

  • kernel/arch/sparc64/include/trap/exception.h

    r721d4e85 raa30c7f  
    3838
    3939#define TT_INSTRUCTION_ACCESS_EXCEPTION         0x08
    40 #define TT_INSTRUCTION_ACCESS_MMU_MISS          0x09
    4140#define TT_INSTRUCTION_ACCESS_ERROR             0x0a
    42 #define TT_IAE_UNAUTH_ACCESS                    0x0b
    43 #define TT_IAE_NFO_PAGE                         0x0c
    4441#define TT_ILLEGAL_INSTRUCTION                  0x10
    4542#define TT_PRIVILEGED_OPCODE                    0x11
    4643#define TT_UNIMPLEMENTED_LDD                    0x12
    4744#define TT_UNIMPLEMENTED_STD                    0x13
    48 #define TT_DAE_INVALID_ASI                      0x14
    49 #define TT_DAE_PRIVILEGE_VIOLATION              0x15
    50 #define TT_DAE_NC_PAGE                          0x16
    51 #define TT_DAE_NFO_PAGE                         0x17
    5245#define TT_FP_DISABLED                          0x20
    5346#define TT_FP_EXCEPTION_IEEE_754                0x21
    … …  
    5649#define TT_DIVISION_BY_ZERO                     0x28
    5750#define TT_DATA_ACCESS_EXCEPTION                0x30
    58 #define TT_DATA_ACCESS_MMU_MISS                 0x31
    5951#define TT_DATA_ACCESS_ERROR                    0x32
    6052#define TT_MEM_ADDRESS_NOT_ALIGNED              0x34

  • kernel/arch/sparc64/include/trap/sun4v/mmu.h

    r721d4e85 raa30c7f  
    3636 */
    3737
    38 #ifndef KERN_sparc64_sun4v_MMU_TRAP_H_
    39 #define KERN_sparc64_sun4v_MMU_TRAP_H_
     38#ifndef KERN_sparc64_SUN4V_MMU_TRAP_H_
     39#define KERN_sparc64_SUN4V_MMU_TRAP_H_
    4040
    4141#include <arch/stack.h>
    … …  
    121121         * but this time its handler accesse memory which IS mapped.
    122122         */
    123         .if (\tl > 0)
    124                 wrpr %g0, 1, %tl
    125         .endif
     1230:
     124.if (\tl > 0)
     125        wrpr %g0, 1, %tl
     126.endif
    126127
    127128        /*

  • kernel/arch/sparc64/include/trap/trap_table.h

    r721d4e85 raa30c7f  
    101101.macro PREEMPTIBLE_HANDLER f
    102102        sethi %hi(\f), %g1
    103         b preemptible_handler
     103        ba %xcc, preemptible_handler
    104104        or %g1, %lo(\f), %g1
    105105.endm

  • kernel/arch/sparc64/src/cpu/sun4v/cpu.c

    r721d4e85 raa30c7f  
    11/*
    22 * Copyright (c) 2005 Jakub Jermar
    3  * Copyright (c) 2009 Pavel Rimsky
    43 * All rights reserved.
    54 *
    … …  
    5251        __hypercall_fast_ret1(0, 0, 0, 0, 0, CPU_MYID, &myid);
    5352
    54         CPU->arch.id = myid;
     53        //MH
     54        //CPU->arch.id = myid;
    5555
    5656        md_node_t node = md_get_root();

  • kernel/arch/sparc64/src/drivers/niagara.c

    r721d4e85 raa30c7f  
    111111static void niagara_putchar(outdev_t *dev, const wchar_t ch, bool silent)
    112112{
    113         if (silent)
    114             return;
    115 
    116113        do_putchar(ch);
    117114        if (ch == '\n')

  • kernel/arch/sparc64/src/mm/sun4u/tlb.c

    r721d4e85 raa30c7f  
    476476}
    477477
    478 void describe_dmmu_fault(void)
     478void dump_sfsr_and_sfar(void)
    479479{
    480480        tlb_sfsr_reg_t sfsr;
    … …  
    499499}
    500500
    501 void dump_sfsr_and_sfar(void)
    502 {
    503         tlb_sfsr_reg_t sfsr;
    504         uintptr_t sfar;
    505 
    506         sfsr.value = dtlb_sfsr_read();
    507         sfar = dtlb_sfar_read();
    508        
    509 #if defined (US)
    510         printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, "
    511             "fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w,
    512             sfsr.ow, sfsr.fv);
    513 #elif defined (US3)
    514         printf("DTLB SFSR: nf=%d, asi=%#x, tm=%d, ft=%#x, e=%d, ct=%d, pr=%d, "
    515             "w=%d, ow=%d, fv=%d\n", sfsr.nf, sfsr.asi, sfsr.tm, sfsr.ft,
    516             sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv);
    517 #endif
    518            
    519         printf("DTLB SFAR: address=%p\n", sfar);
    520        
    521         dtlb_sfsr_write(0);
    522 }
    523 
    524501#if defined (US)
    525502/** Invalidate all unlocked ITLB and DTLB entries. */

  • kernel/arch/sparc64/src/mm/sun4v/as.c

    r721d4e85 raa30c7f  
    11/*
    22 * Copyright (c) 2006 Jakub Jermar
    3  * Copyright (c) 2009 Pavel Rimsky
    43 * All rights reserved.
    54 *
    … …  
    3534
    3635#include <arch/mm/as.h>
    37 #include <arch/mm/pagesize.h>
    3836#include <arch/mm/tlb.h>
    3937#include <genarch/mm/page_ht.h>
    … …  
    4139#include <debug.h>
    4240#include <config.h>
    43 #include <arch/sun4v/hypercall.h>
    4441
    4542#ifdef CONFIG_TSB
    … …  
    8986{
    9087#ifdef CONFIG_TSB
    91         size_t cnt = (TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH;
     88        count_t cnt = (TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH;
    9289        frame_free((uintptr_t) as->arch.tsb_description.tsb_base);
    9390        return cnt;
    … …  
    115112{
    116113        mmu_secondary_context_write(as->asid);
    117 #ifdef CONFIG_TSB       
    118         uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
    119 
    120         ASSERT(as->arch.tsb_description.tsb_base);
    121         uintptr_t tsb = PA2KA(as->arch.tsb_description.tsb_base);
    122                
    123         if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
    124                 /*
    125                  * TSBs were allocated from memory not covered
    126                  * by the locked 4M kernel DTLB entry. We need
    127                  * to map both TSBs explicitly.
    128                  */
    129                 mmu_demap_page(tsb, 0, MMU_FLAG_DTLB);
    130                 dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true);
    131         }
    132 
    133         __hypercall_fast2(MMU_TSB_CTXNON0, 1, KA2PA(&(as->arch.tsb_description)));
    134        
    135 #endif
    136114}
    137115
    … …  
    156134        uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
    157135
    158         ASSERT(as->arch.tsb_description.tsb_base);
     136        ASSERT(as->arch.itsb && as->arch.dtsb);
    159137
    160         uintptr_t tsb = PA2KA(as->arch.tsb_description.tsb_base);
     138        uintptr_t tsb = (uintptr_t) as->arch.itsb;
    161139               
    162140        if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
    … …  
    166144                 * to demap the entry installed by as_install_arch().
    167145                 */
    168                 __hypercall_fast3(MMU_UNMAP_PERM_ADDR, tsb, 0, MMU_FLAG_DTLB);
     146                dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);
    169147        }
    170148#endif

  • kernel/arch/sparc64/src/mm/sun4v/frame.c

    r721d4e85 raa30c7f  
    4141#include <macros.h>
    4242
     43uintptr_t last_frame = NULL;
     44
    4345/** Create memory zones according to information stored in bootinfo.
    4446 *
    … …  
    6668                            SIZE2FRAMES(ALIGN_DOWN(size, FRAME_SIZE)),
    6769                            confdata, 0);
     70                        last_frame = max(last_frame, start + ALIGN_UP(size,
     71                            FRAME_SIZE));
    6872                }
    6973
    … …  
    7680                frame_mark_unavailable(ADDR2PFN(KA2PA(PFN2ADDR(0))), 1);
    7781        }
     82
     83//MH
     84//      end_of_identity = PA2KA(last_frame);
    7885}
    7986

  • kernel/arch/sparc64/src/mm/sun4v/tsb.c

    r721d4e85 raa30c7f  
    11/*
    22 * Copyright (c) 2006 Jakub Jermar
    3  * Copyright (c) 2009 Pavel Rimsky
    43 * All rights reserved.
    54 *
    … …  
    3534
    3635#include <arch/mm/tsb.h>
    37 #include <arch/mm/pagesize.h>
    3836#include <arch/mm/tlb.h>
    3937#include <arch/mm/page.h>
    … …  
    5149 * portions of both TSBs are invalidated at a time.
    5250 *
    53  * @param as    Address space.
    54  * @param page  First page to invalidate in TSB.
    55  * @param pages Number of pages to invalidate. Value of (count_t) -1 means the
    56  *              whole TSB.
     51 * @param as Address space.
     52 * @param page First page to invalidate in TSB.
     53 * @param pages Number of pages to invalidate. Value of (size_t) -1 means the
     54 *      whole TSB.
    5755 */
    5856void tsb_invalidate(as_t *as, uintptr_t page, size_t pages)
    5957{
    60         size_t i0, i;
     58        size_t i0;
     59        size_t i;
    6160        size_t cnt;
    6261       
    63         ASSERT(as->arch.tsb_description.tsb_base);
     62        ASSERT(as->arch.itsb && as->arch.dtsb);
    6463       
    6564        i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
    66         ASSERT(i0 < TSB_ENTRY_COUNT);
     65        ASSERT(i0 < ITSB_ENTRY_COUNT && i0 < DTSB_ENTRY_COUNT);
    6766
    68         if (pages == (size_t) - 1 || (pages) > TSB_ENTRY_COUNT)
    69                 cnt = TSB_ENTRY_COUNT;
     67        if (pages == (size_t) -1 || (pages * 2) > ITSB_ENTRY_COUNT)
     68                cnt = ITSB_ENTRY_COUNT;
    7069        else
    71                 cnt = pages;
     70                cnt = pages * 2;
    7271       
    7372        for (i = 0; i < cnt; i++) {
    74                 ((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[
    75                         (i0 + i) & (TSB_ENTRY_COUNT - 1)].data.v = false;
     73                as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT - 1)].tag.invalid =
     74                    true;
     75                as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT - 1)].tag.invalid =
     76                    true;
    7677        }
    7778}
    … …  
    8081 *
    8182 * @param t     Software PTE.
     83 * @param index Zero if lower 8K-subpage, one if higher 8K subpage.
    8284 */
    83 void itsb_pte_copy(pte_t *t)
     85void itsb_pte_copy(pte_t *t, size_t index)
    8486{
     87#if 0
    8588        as_t *as;
    8689        tsb_entry_t *tsb;
    8790        size_t entry;
    8891
     92        ASSERT(index <= 1);
     93       
    8994        as = t->as;
    90         entry = (t->page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
    91         ASSERT(entry < TSB_ENTRY_COUNT);
    92         tsb = &((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[entry];
     95        entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
     96        ASSERT(entry < ITSB_ENTRY_COUNT);
     97        tsb = &as->arch.itsb[entry];
    9398
    9499        /*
    … …  
    98103         */
    99104
    100         tsb->data.v = false;
     105        tsb->tag.invalid = true;        /* invalidate the entry
     106                                         * (tag target has this
     107                                         * set to 0) */
    101108
    102109        write_barrier();
    103110
     111        tsb->tag.context = as->asid;
     112        /* the shift is bigger than PAGE_WIDTH, do not bother with index  */
    104113        tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
    105 
    106114        tsb->data.value = 0;
    107         tsb->data.nfo = false;
    108         tsb->data.ra = t->frame >> MMU_FRAME_WIDTH;
    109         tsb->data.ie = false;
    110         tsb->data.e = false;
     115        tsb->data.size = PAGESIZE_8K;
     116        tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
    111117        tsb->data.cp = t->c;    /* cp as cache in phys.-idxed, c as cacheable */
    112         tsb->data.cv = false;
    113118        tsb->data.p = t->k;     /* p as privileged, k as kernel */
    114         tsb->data.x = true;
    115         tsb->data.w = false;
    116         tsb->data.size = PAGESIZE_8K;
     119        tsb->data.v = t->p;     /* v as valid, p as present */
    117120       
    118121        write_barrier();
    119122       
    120         tsb->data.v = t->p;     /* v as valid, p as present */
     123        tsb->tag.invalid = false;       /* mark the entry as valid */
     124#endif
    121125}
    122126
    … …  
    124128 *
    125129 * @param t     Software PTE.
     130 * @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
    126131 * @param ro    If true, the mapping is copied read-only.
    127132 */
    128 void dtsb_pte_copy(pte_t *t, bool ro)
     133void dtsb_pte_copy(pte_t *t, size_t index, bool ro)
    129134{
     135#if 0
    130136        as_t *as;
    131137        tsb_entry_t *tsb;
    132138        size_t entry;
     139       
     140        ASSERT(index <= 1);
    133141
    134142        as = t->as;
    135         entry = (t->page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
    136         ASSERT(entry < TSB_ENTRY_COUNT);
    137         tsb = &((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[entry];
     143        entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
     144        ASSERT(entry < DTSB_ENTRY_COUNT);
     145        tsb = &as->arch.dtsb[entry];
    138146
    139147        /*
    … …  
    143151         */
    144152
    145         tsb->data.v = false;
     153        tsb->tag.invalid = true;        /* invalidate the entry
     154                                         * (tag target has this
     155                                         * set to 0) */
    146156
    147157        write_barrier();
    148158
     159        tsb->tag.context = as->asid;
     160        /* the shift is bigger than PAGE_WIDTH, do not bother with index */
    149161        tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
    150 
    151162        tsb->data.value = 0;
    152         tsb->data.nfo = false;
    153         tsb->data.ra = t->frame >> MMU_FRAME_WIDTH;
    154         tsb->data.ie = false;
    155         tsb->data.e = false;
    156         tsb->data.cp = t->c;    /* cp as cache in phys.-idxed, c as cacheable */
     163        tsb->data.size = PAGESIZE_8K;
     164        tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
     165        tsb->data.cp = t->c;
    157166#ifdef CONFIG_VIRT_IDX_DCACHE
    158167        tsb->data.cv = t->c;
    159168#endif /* CONFIG_VIRT_IDX_DCACHE */
    160         tsb->data.p = t->k;     /* p as privileged, k as kernel */
    161         tsb->data.x = true;
     169        tsb->data.p = t->k;             /* p as privileged */
    162170        tsb->data.w = ro ? false : t->w;
    163         tsb->data.size = PAGESIZE_8K;
     171        tsb->data.v = t->p;
    164172       
    165173        write_barrier();
    166174       
    167         tsb->data.v = t->p;     /* v as valid, p as present */
     175        tsb->tag.invalid = false;       /* mark the entry as valid */
     176#endif
    168177}
    169178
    170179/** @}
    171180 */
     181

  • kernel/arch/sparc64/src/sun4v/sparc64.c

    r721d4e85 raa30c7f  
    5050#include <ddi/irq.h>
    5151#include <string.h>
     52
     53//MH
    5254#include <arch/drivers/niagara.h>
    5355

  • kernel/arch/sparc64/src/trap/exception.c

    r721d4e85 raa30c7f  
    162162        fault_if_from_uspace(istate, "%s.", __func__);
    163163        dump_istate(istate);
    164         describe_dmmu_fault();
     164//MH
     165//      dump_sfsr_and_sfar();
    165166        panic("%s.", __func__);
    166167}

  • kernel/arch/sparc64/src/trap/sun4v/trap_table.S

    r721d4e85 raa30c7f  
    4848#include <arch/stack.h>
    4949#include <arch/sun4v/regdef.h>
    50 #include <arch/sun4v/arch.h>
    51 #include <arch/sun4v/cpu.h>
    5250
    5351#define TABLE_SIZE      TRAP_TABLE_SIZE
    … …  
    6260
    6361/* TT = 0x08, TL = 0, instruction_access_exception */
    64 /* TT = 0x08, TL = 0, IAE_privilege_violation on UltraSPARC T2 */
    6562.org trap_table + TT_INSTRUCTION_ACCESS_EXCEPTION*ENTRY_SIZE
    6663.global instruction_access_exception_tl0
    6764instruction_access_exception_tl0:
    68         PREEMPTIBLE_HANDLER instruction_access_exception
    69 
    70 /* TT = 0x09, TL = 0, instruction_access_mmu_miss */
    71 .org trap_table + TT_INSTRUCTION_ACCESS_MMU_MISS*ENTRY_SIZE
    72 .global instruction_access_mmu_miss_handler_tl0
    73         ba fast_instruction_access_mmu_miss_handler_tl0
    74         nop
     65        /*wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
     66        PREEMPTIBLE_HANDLER instruction_access_exception*/
    7567
    7668/* TT = 0x0a, TL = 0, instruction_access_error */
    … …  
    8072        PREEMPTIBLE_HANDLER instruction_access_error
    8173
    82 /* TT = 0x0b, TL = 0, IAE_unauth_access */
    83 .org trap_table + TT_IAE_UNAUTH_ACCESS*ENTRY_SIZE
    84 .global iae_unauth_access_tl0
    85 iae_unauth_access_tl0:
    86         PREEMPTIBLE_HANDLER instruction_access_exception
    87 
    88 /* TT = 0x0c, TL = 0, IAE_nfo_page */
    89 .org trap_table + TT_IAE_NFO_PAGE*ENTRY_SIZE
    90 .global iae_nfo_page_tl0
    91 iae_nfo_page_tl0:
    92         PREEMPTIBLE_HANDLER instruction_access_exception
    93 
    9474/* TT = 0x10, TL = 0, illegal_instruction */
    9575.org trap_table + TT_ILLEGAL_INSTRUCTION*ENTRY_SIZE
    … …  
    11696        PREEMPTIBLE_HANDLER unimplemented_STD
    11797
    118 /* TT = 0x14, TL = 0, DAE_invalid_asi */
    119 .org trap_table + TT_DAE_INVALID_ASI*ENTRY_SIZE
    120 .global dae_invalid_asi_tl0
    121 dae_invalid_asi_tl0:
    122         PREEMPTIBLE_HANDLER data_access_exception
    123 
    124 /* TT = 0x15, TL = 0, DAE_privilege_violation */
    125 .org trap_table + TT_DAE_PRIVILEGE_VIOLATION*ENTRY_SIZE
    126 .global dae_privilege_violation_tl0
    127 dae_privilege_violation_tl0:
    128         PREEMPTIBLE_HANDLER data_access_exception
    129 
    130 /* TT = 0x16, TL = 0, DAE_nc_page */
    131 .org trap_table + TT_DAE_NC_PAGE*ENTRY_SIZE
    132 .global dae_nc_page_tl0
    133 dae_nc_page_tl0:
    134         PREEMPTIBLE_HANDLER data_access_exception
    135 
    136 /* TT = 0x17, TL = 0, DAE_nfo_page */
    137 .org trap_table + TT_DAE_NFO_PAGE*ENTRY_SIZE
    138 .global dae_nfo_page_tl0
    139 dae_nfo_page_tl0:
    140         PREEMPTIBLE_HANDLER data_access_exception
    141 
    14298/* TT = 0x20, TL = 0, fb_disabled handler */
    14399.org trap_table + TT_FP_DISABLED*ENTRY_SIZE
    … …  
    177133
    178134/* TT = 0x30, TL = 0, data_access_exception */
    179 /* TT = 0x30, TL = 0, DAE_side_effect_page for UltraPSARC T2 */
    180135.org trap_table + TT_DATA_ACCESS_EXCEPTION*ENTRY_SIZE
    181136.global data_access_exception_tl0
    182137data_access_exception_tl0:
     138        wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
    183139        PREEMPTIBLE_HANDLER data_access_exception
    184 
    185 /* TT = 0x31, TL = 0, data_access_mmu_miss */
    186 .org trap_table + TT_DATA_ACCESS_MMU_MISS*ENTRY_SIZE
    187 .global data_access_mmu_miss_tl0
    188 data_access_mmu_miss_tl0:
    189         ba fast_data_access_mmu_miss_handler_tl0
    190         nop
    191140
    192141/* TT = 0x32, TL = 0, data_access_error */
    … …  
    322271        INTERRUPT_LEVEL_N_HANDLER 15
    323272
     273/* TT = 0x60, TL = 0, interrupt_vector_trap handler */
     274.org trap_table + TT_INTERRUPT_VECTOR_TRAP*ENTRY_SIZE
     275.global interrupt_vector_trap_handler_tl0
     276interrupt_vector_trap_handler_tl0:
     277        INTERRUPT_VECTOR_TRAP_HANDLER
     278
    324279/* TT = 0x64, TL = 0, fast_instruction_access_MMU_miss */
    325280.org trap_table + TT_FAST_INSTRUCTION_ACCESS_MMU_MISS*ENTRY_SIZE
    … …  
    339294fast_data_access_protection_handler_tl0:
    340295        FAST_DATA_ACCESS_PROTECTION_HANDLER 0
    341 
    342 /* TT = 0x7c, TL = 0, cpu_mondo */
    343 .org trap_table + TT_CPU_MONDO*ENTRY_SIZE
    344 .global cpu_mondo_handler_tl0
    345 cpu_mondo_handler_tl0:
    346 /* PREEMPTIBLE_HANDLER cpu_mondo */
    347296
    348297/* TT = 0x80, TL = 0, spill_0_normal handler */
    … …  
    403352
    404353/* TT = 0x08, TL > 0, instruction_access_exception */
    405 /* TT = 0x08, TL > 0, IAE_privilege_violation on UltraSPARC T2 */
    406354.org trap_table + (TT_INSTRUCTION_ACCESS_EXCEPTION+512)*ENTRY_SIZE
    407355.global instruction_access_exception_tl1
    408356instruction_access_exception_tl1:
    409357        wrpr %g0, 1, %tl
     358        wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
    410359        PREEMPTIBLE_HANDLER instruction_access_exception
    411 
    412 /* TT = 0x09, TL > 0, instruction_access_mmu_miss */
    413 .org trap_table + (TT_INSTRUCTION_ACCESS_MMU_MISS+512)*ENTRY_SIZE
    414 .global instruction_access_mmu_miss_handler_tl1
    415         wrpr %g0, 1, %tl
    416         ba fast_instruction_access_mmu_miss_handler_tl0
    417         nop
    418360
    419361/* TT = 0x0a, TL > 0, instruction_access_error */
    … …  
    424366        PREEMPTIBLE_HANDLER instruction_access_error
    425367
    426 /* TT = 0x0b, TL > 0, IAE_unauth_access */
    427 .org trap_table + (TT_IAE_UNAUTH_ACCESS+512)*ENTRY_SIZE
    428 .global iae_unauth_access_tl1
    429 iae_unauth_access_tl1:
    430         wrpr %g0, 1, %tl
    431         PREEMPTIBLE_HANDLER instruction_access_exception
    432 
    433 /* TT = 0x0c, TL > 0, IAE_nfo_page */
    434 .org trap_table + (TT_IAE_NFO_PAGE+512)*ENTRY_SIZE
    435 .global iae_nfo_page_tl1
    436 iae_nfo_page_tl1:
    437         wrpr %g0, 1, %tl
    438         PREEMPTIBLE_HANDLER instruction_access_exception
    439 
    440368/* TT = 0x10, TL > 0, illegal_instruction */
    441369.org trap_table + (TT_ILLEGAL_INSTRUCTION+512)*ENTRY_SIZE
    … …  
    445373        PREEMPTIBLE_HANDLER illegal_instruction
    446374
    447 /* TT = 0x14, TL > 0, DAE_invalid_asi */
    448 .org trap_table + (TT_DAE_INVALID_ASI+512)*ENTRY_SIZE
    449 .global dae_invalid_asi_tl1
    450 dae_invalid_asi_tl1:
    451         wrpr %g0, 1, %tl
    452         PREEMPTIBLE_HANDLER data_access_exception
    453 
    454 /* TT = 0x15, TL > 0, DAE_privilege_violation */
    455 .org trap_table + (TT_DAE_PRIVILEGE_VIOLATION+512)*ENTRY_SIZE
    456 .global dae_privilege_violation_tl1
    457 dae_privilege_violation_tl1:
    458         wrpr %g0, 1, %tl
    459         PREEMPTIBLE_HANDLER data_access_exception
    460 
    461 /* TT = 0x16, TL > 0, DAE_nc_page */
    462 .org trap_table + (TT_DAE_NC_PAGE+512)*ENTRY_SIZE
    463 .global dae_nc_page_tl1
    464 dae_nc_page_tl1:
    465         wrpr %g0, 1, %tl
    466         PREEMPTIBLE_HANDLER data_access_exception
    467 
    468 /* TT = 0x17, TL > 0, DAE_nfo_page */
    469 .org trap_table + (TT_DAE_NFO_PAGE+512)*ENTRY_SIZE
    470 .global dae_nfo_page_tl1
    471 dae_nfo_page_tl1:
    472         wrpr %g0, 1, %tl
    473         PREEMPTIBLE_HANDLER data_access_exception
    474 
    475375/* TT = 0x24, TL > 0, clean_window handler */
    476376.org trap_table + (TT_CLEAN_WINDOW+512)*ENTRY_SIZE
    … …  
    490390.global data_access_exception_tl1
    491391data_access_exception_tl1:
    492         /*wrpr %g0, 1, %tl
     392        wrpr %g0, 1, %tl
    493393        wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
    494         PREEMPTIBLE_HANDLER data_access_exception*/
    495 
    496 /* TT = 0x31, TL > 0, data_access_mmu_miss */
    497 .org trap_table + (TT_DATA_ACCESS_MMU_MISS+512)*ENTRY_SIZE
    498 .global data_access_mmu_miss_tl1
    499 data_access_mmu_miss_tl1:
    500         ba fast_data_access_mmu_miss_handler_tl1
    501         nop
    502 
     394        PREEMPTIBLE_HANDLER data_access_exception
    503395
    504396/* TT = 0x32, TL > 0, data_access_error */
    … …  
    527419fast_data_access_protection_handler_tl1:
    528420        FAST_DATA_ACCESS_PROTECTION_HANDLER 1
    529 
    530 /* TT = 0x7c, TL > 0, cpu_mondo */
    531 .org trap_table + (TT_CPU_MONDO+512)*ENTRY_SIZE
    532 .global cpu_mondo_handler_tl1
    533 cpu_mondo_handler_tl1:
    534         wrpr %g0, %tl
    535 /*      PREEMPTIBLE_HANDLER cpu_mondo */
    536421
    537422/* TT = 0x80, TL > 0, spill_0_normal handler */
    … …  
    775660.endm
    776661
     662
     663#if 0
    777664/*
    778665 * Preemptible trap handler for handling traps from kernel.
    … …  
    790677        nop                                     ! it will be easy to find
    791678
     679        /* prevent unnecessary CLEANWIN exceptions */
     680        wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(0), %wstate
     6811:
     682        /*
     683         * Prevent SAVE instruction from causing a spill exception. If the
     684         * CANSAVE register is zero, explicitly spill register window
     685         * at CWP + 2.
     686         */
     687
     688        rdpr %cansave, %g3
     689        brnz %g3, 2f
     690        nop
     691        INLINE_SPILL %g3, %g4
     692
     6932:
     694        /* ask for new register window */
     695        save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
     696
     697        /* copy higher level routine's address and its argument */
     698        mov %g1, %l0
     699        mov %g2, %o0
     700
     701        /*
     702         * Save TSTATE, TPC and TNPC aside.
     703         */
     704        rdpr %tstate, %g1
     705        rdpr %tpc, %g2
     706        rdpr %tnpc, %g3
     707
     708        stx %g1, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TSTATE]
     709        stx %g2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC]
     710        stx %g3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC]
     711
     712        /*
     713         * Save the Y register.
     714         * This register is deprecated according to SPARC V9 specification
     715         * and is only present for backward compatibility with previous
     716         * versions of the SPARC architecture.
     717         * Surprisingly, gcc makes use of this register without a notice.
     718         */
     719        rd %y, %g4
     720        stx %g4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y]
     721
     722        /* switch to TL = 0, explicitly enable FPU */
     723        wrpr %g0, 0, %tl
     724        wrpr %g0, 0, %gl
     725        wrpr %g0, PSTATE_PRIV_BIT | PSTATE_PEF_BIT, %pstate
     726
     727        /* g1 -> l1, ..., g7 -> l7 */
     728        SAVE_GLOBALS
     729
     730        /* call higher-level service routine, pass istate as its 2nd parameter */
     731        call %l0
     732        add %sp, PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC, %o1
     733
     734        /* l1 -> g1, ..., l7 -> g7 */
     735        RESTORE_GLOBALS
     736
     737        /* we must prserve the PEF bit */
     738        rdpr %pstate, %l1
     739
     740        /* TL := 1, GL := 1 */
     741        wrpr %g0, PSTATE_PRIV_BIT, %pstate
     742        wrpr %g0, 1, %tl
     743        wrpr %g0, 1, %gl
     744
     745        /* Read TSTATE, TPC and TNPC from saved copy. */
     746        ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TSTATE], %g1
     747        ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC], %g2
     748        ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC], %g3
     749
     750        /* Copy PSTATE.PEF to the in-register copy of TSTATE. */
     751        and %l1, PSTATE_PEF_BIT, %l1
     752        sllx %l1, TSTATE_PSTATE_SHIFT, %l1
     753        sethi %hi(TSTATE_PEF_BIT), %g4          ! reset the PEF bit to 0 ...
     754        andn %g1, %g4, %g1
     755        or %g1, %l1, %g1                        ! ... "or" it with saved PEF
     756
     757        /* Restore TSTATE, TPC and TNPC from saved copies. */
     758        wrpr %g1, 0, %tstate
     759        wrpr %g2, 0, %tpc
     760        wrpr %g3, 0, %tnpc
     761
     762        /* Restore Y. */
     763        ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y], %g4
     764        wr %g4, %y
     765       
     766        /* If TSTATE.CWP + 1 == CWP, then we do not have to fix CWP. */
     767        and %g1, TSTATE_CWP_MASK, %l0
     768        inc %l0
     769        and %l0, NWINDOWS - 1, %l0      ! %l0 mod NWINDOWS
     770        rdpr %cwp, %l1
     771        cmp %l0, %l1
     772        bz 4f                           ! CWP is ok
     773        nop
     774
     7753:
     776        /*
     777         * Fix CWP.
     778         * In order to recapitulate, the input registers in the current
     779         * window are the output registers of the window to which we want
     780         * to restore. Because the fill trap fills only input and local
     781         * registers of a window, we need to preserve those output
     782         * registers manually.
     783         */
     784        mov %sp, %g2
     785        stx %i0, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I0]
     786        stx %i1, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I1]
     787        stx %i2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I2]
     788        stx %i3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I3]
     789        stx %i4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I4]
     790        stx %i5, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I5]
     791        stx %i6, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6]
     792        stx %i7, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7]
     793        wrpr %l0, 0, %cwp
     794        mov %g2, %sp
     795        ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I0], %i0
     796        ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I1], %i1
     797        ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I2], %i2
     798        ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I3], %i3
     799        ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I4], %i4
     800        ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I5], %i5
     801        ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6], %i6
     802        ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7], %i7
     803
     8044:
     805        /*
     806         * Prevent RESTORE instruction from causing a fill exception. If the
     807         * CANRESTORE register is zero, explicitly fill register window
     808         * at CWP - 1.
     809         */
     810        rdpr %canrestore, %g1
     811        brnz %g1, 5f
     812        nop
     813        INLINE_FILL %g3, %g4
     814
     8155:
     816        restore
     817
     818        retry
     819.endm
     820
     821#endif
     822
     823/*
     824 * Preemptible trap handler for handling traps from kernel.
     825 */
     826.macro PREEMPTIBLE_HANDLER_KERNEL
     827
     828        /*
     829         * ASSERT(%tl == 1)
     830         */
     831        rdpr %tl, %g3
     832        cmp %g3, 1
     833        be 1f
     834        nop
     8350:      ba 0b                                   ! this is for debugging, if we ever get here
     836        nop                                     ! it will be easy to find
     837
    7928381:
    793839        /* prevent unnecessary CLEANWIN exceptions */
    … …  
    826872        retry
    827873.endm
     874
     875
    828876
    829877/*
    … …  
    10441092        and %g1, NWINDOWS - 1, %g1
    10451093        wrpr %g1, 0, %cwp                       ! CWP--
    1046        
     1094
    10471095.if \is_syscall
    10481096        done
    … …  
    10521100
    10531101.endm
     1102
     1103
    10541104
    10551105/* Preemptible trap handler for TL=1.
    … …  
    10821132trap_instruction_handler:
    10831133        PREEMPTIBLE_HANDLER_TEMPLATE 1
     1134

  • kernel/generic/include/errno.h

    r721d4e85 raa30c7f  
    5757#define EADDRNOTAVAIL   -12     /* Address not available. */
    5858#define ETIMEOUT        -13     /* Timeout expired */
     59//MH
     60#ifndef EINVAL
    5961#define EINVAL          -14     /* Invalid value */
     62#endif
     63#ifndef EBUSY
    6064#define EBUSY           -15     /* Resource is busy */
     65#endif
    6166#define EOVERFLOW       -16     /* The result does not fit its size. */
    6267#define EINTR           -17     /* Operation was interrupted. */
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