Changes in / [b3ab8f7:aac1c417] in mainline


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Files:
18 deleted
34 edited

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  • HelenOS.config

    rb3ab8f7 raac1c417  
    6565@ "testarm" GXEmul Testarm
    6666@ "integratorcp" Integratorcp
    67 @ "beagleboardxm" BeogleBoard-xM
    6867! [PLATFORM=arm32] MACHINE (choice)
    6968
    … …  
    8786! [PLATFORM=sparc64&MACHINE=generic] PROCESSOR (choice)
    8887
    89 % CPU type
    90 @ "armv4" ARMv4
    91 ! [PLATFORM=arm32&(MACHINE=gta02|MACHINE=gxemul)] PROCESSOR (choice)
    92 
    93 % CPU type
    94 @ "armv5" ARMv5
    95 ! [PLATFORM=arm32&MACHINE=integratorcp] PROCESSOR (choice)
    96 
    97 % CPU type
    98 @ "armv7_a" ARMv7-A
    99 ! [PLATFORM=arm32&MACHINE=beagleboardxm] PROCESSOR (choice)
    100 
    101 
    10288% RAM disk format
    10389@ "tmpfs" TMPFS image
    … …  
    420406% Output device class
    421407@ "generic" Monitor or serial line
    422 ! [PLATFORM=arm32&(MACHINE=gta02|MACHINE=integratorcp|MACHINE=beagleboardxm)] CONFIG_HID_OUT (choice)
     408! [PLATFORM=arm32&(MACHINE=gta02|MACHINE=integratorcp)] CONFIG_HID_OUT (choice)
    423409
    424410% Output device class
    … …  
    480466! [PLATFORM=arm32&MACHINE=gta02] CONFIG_S3C24XX_IRQC (y)
    481467
    482 % Support for TI AMDM37X on-chip UART
    483 ! [(CONFIG_HID_OUT=generic|CONFIG_HID_OUT=serial)&PLATFORM=arm32&MACHINE=beagleboardxm] CONFIG_AMDM37X_UART (y/n)
    484 
    485468% Support for i8042 controller
    486469! [CONFIG_PC_KBD=y] CONFIG_I8042 (y)
    … …  
    502485
    503486% Serial line input module
    504 ! [CONFIG_DSRLNIN=y|(PLATFORM=arm32&MACHINE=gta02)|(PLATFORM=arm32&MACHINE=integratorcp&CONFIG_ARM926_UART=y)|(PLATFORM=arm32&MACHINE=beagleboardxm&CONFIG_AMDM37X_UART=y)|(PLATFORM=ia64&MACHINE=i460GX&CONFIG_NS16550=y)|(PLATFORM=ia64&MACHINE=ski)|(PLATFORM=sparc64&PROCESSOR=sun4v)] CONFIG_SRLN (y)
     487! [CONFIG_DSRLNIN=y|(PLATFORM=arm32&MACHINE=gta02)|(PLATFORM=arm32&MACHINE=integratorcp&CONFIG_ARM926_UART=y)|(PLATFORM=ia64&MACHINE=i460GX&CONFIG_NS16550=y)|(PLATFORM=ia64&MACHINE=ski)|(PLATFORM=sparc64&PROCESSOR=sun4v)] CONFIG_SRLN (y)
    505488
    506489% EGA support
    … …  
    538521@ "1920x1080"
    539522@ "1920x1200"
    540 ! [(PLATFORM=ia32|PLATFORM=amd64|MACHINE=beagleboardxm)&CONFIG_HID_OUT!=none&CONFIG_FB=y] CONFIG_BFB_MODE (choice)
     523! [(PLATFORM=ia32|PLATFORM=amd64)&CONFIG_HID_OUT!=none&CONFIG_FB=y] CONFIG_BFB_MODE (choice)
    541524
    542525% Default framebuffer depth
    … …  
    544527@ "16"
    545528@ "24"
    546 ! [(PLATFORM=ia32|PLATFORM=amd64|MACHINE=beagleboardxm)&CONFIG_HID_OUT!=none&CONFIG_FB=y] CONFIG_BFB_BPP (choice)
     529! [(PLATFORM=ia32|PLATFORM=amd64)&CONFIG_HID_OUT!=none&CONFIG_FB=y] CONFIG_BFB_BPP (choice)
    547530
    548531% Start AP processors by the loader
    … …  
    612595@ "efi" GRUB for UEFI
    613596! [PLATFORM=ia32|PLATFORM=amd64] GRUB_ARCH (choice)
    614 
    615 % uImage OS type
    616 @ "2" NetBSD stage 2 boot loader
    617 ! [PLATFORM=arm32&MACHINE=beagleboardxm] UIMAGE_OS (choice)
    618 
    619 % uImage OS type
    620 @ "5" Linux kernel
    621 ! [PLATFORM=arm32&MACHINE!=beagleboardxm] UIMAGE_OS (choice)

  • boot/Makefile.uboot

    rb3ab8f7 raac1c417  
    4040
    4141$(POST_OUTPUT): $(BIN_OUTPUT)
    42         $(MKUIMAGE) -name "$(IMAGE_NAME)" -laddr $(LADDR) -saddr $(SADDR) -ostype $(UIMAGE_OS) $< $@
     42        $(MKUIMAGE) -name "$(IMAGE_NAME)" -laddr 0x30008000 -saddr 0x30008000 $< $@
    4343
    4444clean:

  • boot/arch/arm32/Makefile.inc

    rb3ab8f7 raac1c417  
    3030        BOOT_OUTPUT = image.boot
    3131        POST_OUTPUT = $(ROOT_PATH)/uImage.bin
    32         LADDR = 0x30008000
    33         SADDR = 0x30008000
    34         POSTBUILD = Makefile.uboot
    35 endif
    36 
    37 ifeq ($(MACHINE), beagleboardxm)
    38         BOOT_OUTPUT = image.boot
    39         POST_OUTPUT = $(ROOT_PATH)/uImage.bin
    40         LADDR = 0x80000000
    41         SADDR = 0x80000000
    4232        POSTBUILD = Makefile.uboot
    4333endif
    … …  
    4939BITS = 32
    5040ENDIANESS = LE
    51 EXTRA_CFLAGS = -march=$(subst _,-,$(PROCESSOR)) -mno-unaligned-access
     41EXTRA_CFLAGS = -march=armv4
    5242
    53 ifeq ($(MACHINE), gta02)
    5443RD_SRVS_ESSENTIAL += \
    5544        $(USPACE_PATH)/srv/hid/s3c24xx_ts/s3c24xx_ts \
    5645        $(USPACE_PATH)/srv/hw/char/s3c24xx_uart/s3c24xx_uart
    57 endif
    5846
    59 ifeq ($(MACHINE), gxemul)
    6047RD_SRVS_NON_ESSENTIAL += \
    6148        $(USPACE_PATH)/srv/bd/gxe_bd/gxe_bd
    62 endif
    63 
    64 RD_DRVS += \
    65         infrastructure/rootamdm37x \
    66         bus/usb/ehci \
    67         bus/usb/ohci \
    68         bus/usb/usbflbk \
    69         bus/usb/usbhub \
    70         bus/usb/usbhid \
    71         bus/usb/usbmast \
    72         bus/usb/usbmid
    7349
    7450SOURCES = \

  • boot/arch/arm32/include/arch.h

    rb3ab8f7 raac1c417  
    4242#ifdef MACHINE_gta02
    4343#define BOOT_BASE       0x30008000
    44 #elif defined MACHINE_beagleboardxm
    45 #define BOOT_BASE       0x80000000
    4644#else
    4745#define BOOT_BASE       0x00000000
    … …  
    5048#define BOOT_OFFSET     (BOOT_BASE + 0xa00000)
    5149
    52 #ifdef MACHINE_beagleboardxm
    53         #define PA_OFFSET 0
     50#ifndef __ASM__
     51        #define PA2KA(addr)  (((uintptr_t) (addr)) + 0x80000000)
    5452#else
    55         #define PA_OFFSET 0x80000000
     53        #define PA2KA(addr)  ((addr) + 0x80000000)
    5654#endif
    57 
    58 #ifndef __ASM__
    59         #define PA2KA(addr)  (((uintptr_t) (addr)) + PA_OFFSET)
    60 #else
    61         #define PA2KA(addr)  ((addr) + PA_OFFSET)
    62 #endif
    63 
    6455
    6556#endif

  • boot/arch/arm32/include/main.h

    rb3ab8f7 raac1c417  
    4040/** Address where characters to be printed are expected. */
    4141
    42 
    43 /** BeagleBoard-xM UART register address
    44  *
    45  * This is UART3 of AM/DM37x CPU
    46  */
    47 #define BBXM_SCONS_THR          0x49020000
    48 #define BBXM_SCONS_SSR          0x49020044
    49 
    50 /* Check this bit before writing (tx fifo full) */
    51 #define BBXM_THR_FULL           0x00000001
    52 
    53 
    5442/** GTA02 serial console UART register addresses.
    5543 *

  • boot/arch/arm32/include/mm.h

    rb3ab8f7 raac1c417  
    5858        unsigned int bufferable : 1;
    5959        unsigned int cacheable : 1;
    60         unsigned int xn : 1;
     60        unsigned int impl_specific : 1;
    6161        unsigned int domain : 4;
    6262        unsigned int should_be_zero_1 : 1;
    63         unsigned int access_permission_0 : 2;
    64         unsigned int tex : 3;
    65         unsigned int access_permission_1 : 2;
    66         unsigned int non_global : 1;
    67         unsigned int should_be_zero_2 : 1;
    68         unsigned int non_secure : 1;
     63        unsigned int access_permission : 2;
     64        unsigned int should_be_zero_2 : 8;
    6965        unsigned int section_base_addr : 12;
    7066} __attribute__((packed)) pte_level0_section_t;

  • boot/arch/arm32/src/mm.c

    rb3ab8f7 raac1c417  
    5454{
    5555        pte->descriptor_type = PTE_DESCRIPTOR_SECTION;
    56         pte->bufferable = 1;
     56        pte->bufferable = 0;
    5757        pte->cacheable = 0;
    58         pte->xn = 0;
     58        pte->impl_specific = 0;
    5959        pte->domain = 0;
    6060        pte->should_be_zero_1 = 0;
    61         pte->access_permission_0 = PTE_AP_USER_NO_KERNEL_RW;
    62         pte->tex = 0;
    63         pte->access_permission_1 = 0;
    64         pte->non_global = 0;
     61        pte->access_permission = PTE_AP_USER_NO_KERNEL_RW;
    6562        pte->should_be_zero_2 = 0;
    66         pte->non_secure = 0;
    6763        pte->section_base_addr = frame;
    6864}
    … …  
    7167static void init_boot_pt(void)
    7268{
    73         const pfn_t split_page = PTL0_ENTRIES;
     69        pfn_t split_page = 0x800;
     70       
    7471        /* Create 1:1 virtual-physical mapping (in lower 2 GB). */
    7572        pfn_t page;
    … …  
    8178         * (upper 2 GB), physical addresses start from 0.
    8279         */
    83         /* BeagleBoard-xM (DM37x) memory starts at 2GB border,
    84          * thus mapping only lower 2GB is not not enough.
    85          * Map entire AS 1:1 instead and hope it works. */
    8680        for (page = split_page; page < PTL0_ENTRIES; page++)
    87 #ifndef MACHINE_beagleboardxm
    8881                init_ptl0_section(&boot_pt[page], page - split_page);
    89 #else
    90                 init_ptl0_section(&boot_pt[page], page);
    91 #endif
    9282       
    9383        asm volatile (
    … …  
    10595                /* Behave as a client of domains */
    10696                "ldr r0, =0x55555555\n"
    107                 "mcr p15, 0, r0, c3, c0, 0\n"
     97                "mcr p15, 0, r0, c3, c0, 0\n" 
    10898               
    109 #ifdef PROCESSOR_armv7_a
    110                 /* Read Auxiliary control register */
    111                 "mrc p15, 0, r0, c1, c0, 1\n"
    112                 /* Mask to enable L2 cache */
    113                 "ldr r1, =0x00000002\n"
    114                 "orr r0, r0, r1\n"
    115                 /* Store Auxiliary control register */
    116                 "mrc p15, 0, r0, c1, c0, 1\n"
    117 #endif
    11899                /* Current settings */
    119100                "mrc p15, 0, r0, c1, c0, 0\n"
    120101               
    121 #ifdef PROCESSOR_armv7_a
    122                 /* Mask to enable paging, caching */
    123                 "ldr r1, =0x00000005\n"
    124 #else
    125102                /* Mask to enable paging */
    126103                "ldr r1, =0x00000001\n"
    127 #endif
    128104                "orr r0, r0, r1\n"
    129105               

  • boot/arch/arm32/src/putchar.c

    rb3ab8f7 raac1c417  
    4040#include <putchar.h>
    4141#include <str.h>
    42 
    43 #ifdef MACHINE_beagleboardxm
    44 
    45 /** Send a byte to the amdm37x serial console.
    46  *
    47  * @param byte          Byte to send.
    48  */
    49 static void scons_sendb_bbxm(uint8_t byte)
    50 {
    51         volatile uint32_t *thr =
    52             (volatile uint32_t *)BBXM_SCONS_THR;
    53         volatile uint32_t *ssr =
    54             (volatile uint32_t *)BBXM_SCONS_SSR;
    55 
    56         /* Wait until transmitter is empty. */
    57         while ((*ssr & BBXM_THR_FULL) == 1) ;
    58 
    59         /* Transmit byte. */
    60         *thr = (uint32_t) byte;
    61 }
    62 
    63 #endif
    6442
    6543#ifdef MACHINE_gta02
    … …  
    11997static void scons_sendb(uint8_t byte)
    12098{
    121 #ifdef MACHINE_beagleboardxm
    122         scons_sendb_bbxm(byte);
    123 #endif
    12499#ifdef MACHINE_gta02
    125100        scons_sendb_gta02(byte);

  • defaults/arm32/gta02/Makefile.config

    rb3ab8f7 raac1c417  
    33
    44# RAM disk format
    5 RDFMT = fat
     5RDFMT = tmpfs

  • kernel/arch/arm32/Makefile.inc

    rb3ab8f7 raac1c417  
    3333ATSIGN = %
    3434
    35 GCC_CFLAGS += -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR)) -mno-unaligned-access
     35GCC_CFLAGS += -march=armv4 -fno-omit-frame-pointer -mapcs-frame
    3636
    3737BITS = 32
    … …  
    7474endif
    7575
    76 ifeq ($(MACHINE),beagleboardxm)
    77         ARCH_SOURCES += arch/$(KARCH)/src/mach/beagleboardxm/beagleboardxm.c
    78 endif
    79 
    8076ifeq ($(CONFIG_PL050),y)
    8177        ARCH_SOURCES += genarch/src/drivers/pl050/pl050.c

  • kernel/arch/arm32/_link.ld.in

    rb3ab8f7 raac1c417  
    99#ifdef MACHINE_gta02
    1010#define KERNEL_LOAD_ADDRESS 0xb0a08000
    11 #elif defined MACHINE_beagleboardxm
    12 #define KERNEL_LOAD_ADDRESS 0x80a00000
    1311#else
    1412#define KERNEL_LOAD_ADDRESS 0x80a00000

  • kernel/arch/arm32/include/asm.h

    rb3ab8f7 raac1c417  
    4343#include <trace.h>
    4444
    45 /** No such instruction on old ARM to sleep CPU.
    46  *
    47  * ARMv7 introduced wait for event and wait for interrupt (wfe/wfi).
    48  * ARM920T has custom coprocessor action to do the same. See ARM920T Technical
    49  * Reference Manual ch 4.9 p. 4-23 (103 in the PDF)
    50  */
     45/** No such instruction on ARM to sleep CPU. */
    5146NO_TRACE static inline void cpu_sleep(void)
    5247{
    53 #ifdef PROCESSOR_armv7_a
    54         asm volatile ( "wfe" :: );
    55 #elif defined(MACHINE_gta02)
    56         asm volatile ( "mcr p15,0,R0,c7,c0,4" :: );
    57 #endif
    5848}
    5949

  • kernel/arch/arm32/include/barrier.h

    rb3ab8f7 raac1c417  
    4747#define write_barrier()   asm volatile ("" ::: "memory")
    4848
    49 /*
    50  * There are multiple ways ICache can be implemented on ARM machines. Namely
    51  * PIPT, VIPT, and ASID and VMID tagged VIVT (see ARM Architecture Reference
    52  * Manual B3.11.2 (p. 1383).  However, CortexA8 Manual states: "For maximum
    53  * compatibility across processors, ARM recommends that operating systems target
    54  * the ARMv7 base architecture that uses ASID-tagged VIVT instruction caches,
    55  * and do not assume the presence of the IVIPT extension. Software that relies
    56  * on the IVIPT extension might fail in an unpredictable way on an ARMv7
    57  * implementation that does not include the IVIPT extension." (7.2.6 p. 245).
    58  * Only PIPT invalidates cache for all VA aliases if one block is invalidated.
    59  *
    60  * @note: Supporting ASID and VMID tagged VIVT may need to add ICache
    61  * maintenance to other places than just smc.
    62  */
    63 
    64 /* Available on both all supported arms,
    65  * invalidates entire ICache so the written value does not matter. */
    66 #define smc_coherence(a) asm volatile ( "mcr p15, 0, r0, c7, c5, 0")
    67 #define smc_coherence_block(a, l) smc_coherence(a)
    68 
     49#define smc_coherence(a)
     50#define smc_coherence_block(a, l)
    6951
    7052#endif

  • kernel/arch/arm32/include/cpu.h

    rb3ab8f7 raac1c417  
    4141
    4242
    43 /** Struct representing ARM CPU identification. */
     43/** Struct representing ARM CPU identifiaction. */
    4444typedef struct {
    4545        /** Implementator (vendor) number. */

  • kernel/arch/arm32/include/machine_func.h

    rb3ab8f7 raac1c417  
    108108extern size_t machine_get_irq_count(void);
    109109
    110 extern const char * machine_get_platform_name(void);
    111 
    112110#endif
    113111

  • kernel/arch/arm32/include/mm/frame.h

    rb3ab8f7 raac1c417  
    4848#ifdef MACHINE_gta02
    4949#define BOOT_PAGE_TABLE_ADDRESS  0x30010000
    50 #elif defined MACHINE_beagleboardxm
    51 #define BOOT_PAGE_TABLE_ADDRESS  0x80008000
    5250#else
    5351#define BOOT_PAGE_TABLE_ADDRESS  0x00008000
    … …  
    5957#ifdef MACHINE_gta02
    6058#define PHYSMEM_START_ADDR      0x30008000
    61 #elif defined MACHINE_beagleboardxm
    62 #define PHYSMEM_START_ADDR      0x80000000
    6359#else
    6460#define PHYSMEM_START_ADDR      0x00000000

  • kernel/arch/arm32/include/mm/page.h

    rb3ab8f7 raac1c417  
    4646#define PAGE_SIZE       FRAME_SIZE
    4747
    48 #ifdef MACHINE_beagleboardxm
    49 #ifndef __ASM__
    50 #       define KA2PA(x) ((uintptr_t) (x))
    51 #       define PA2KA(x) ((uintptr_t) (x))
    52 #else
    53 #       define KA2PA(x) (x)
    54 #       define PA2KA(x) (x)
    55 #endif
    56 #else
    5748#ifndef __ASM__
    5849#       define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
    … …  
    6253#       define PA2KA(x) ((x) + 0x80000000)
    6354#endif
    64 #endif
    6555
    6656/* Number of entries in each level. */
    67 #define PTL0_ENTRIES_ARCH       (1 << 12)       /* 4096 */
    68 #define PTL1_ENTRIES_ARCH       0
    69 #define PTL2_ENTRIES_ARCH       0
     57#define PTL0_ENTRIES_ARCH       (1 << 12)       /* 4096 */
     58#define PTL1_ENTRIES_ARCH       0
     59#define PTL2_ENTRIES_ARCH       0
    7060/* coarse page tables used (256 * 4 = 1KB per page) */
    71 #define PTL3_ENTRIES_ARCH       (1 << 8)        /* 256 */
     61#define PTL3_ENTRIES_ARCH       (1 << 8)        /* 256 */
    7262
    7363/* Page table sizes for each level. */
    74 #define PTL0_SIZE_ARCH          FOUR_FRAMES
    75 #define PTL1_SIZE_ARCH          0
    76 #define PTL2_SIZE_ARCH          0
    77 #define PTL3_SIZE_ARCH          ONE_FRAME
     64#define PTL0_SIZE_ARCH          FOUR_FRAMES
     65#define PTL1_SIZE_ARCH          0
     66#define PTL2_SIZE_ARCH          0
     67#define PTL3_SIZE_ARCH          ONE_FRAME
    7868
    7969/* Macros calculating indices into page tables for each level. */
    80 #define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 20) & 0xfff)
    81 #define PTL1_INDEX_ARCH(vaddr)  0
    82 #define PTL2_INDEX_ARCH(vaddr)  0
    83 #define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x0ff)
     70#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 20) & 0xfff)
     71#define PTL1_INDEX_ARCH(vaddr)  0
     72#define PTL2_INDEX_ARCH(vaddr)  0
     73#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x0ff)
    8474
    8575/* Get PTE address accessors for each level. */
    8676#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
    87         ((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10))
     77        ((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10))
    8878#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
    89         (ptl1)
     79        (ptl1)
    9080#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
    91         (ptl2)
     81        (ptl2)
    9282#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
    93         ((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12))
     83        ((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12))
    9484
    9585/* Set PTE address accessors for each level. */
    9686#define SET_PTL0_ADDRESS_ARCH(ptl0) \
    97         (set_ptl0_addr((pte_t *) (ptl0)))
     87        (set_ptl0_addr((pte_t *) (ptl0)))
    9888#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
    99         (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10)
     89        (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10)
    10090#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
    10191#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
    10292#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
    103         (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12)
     93        (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12)
    10494
    10595/* Get PTE flags accessors for each level. */
    10696#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
    107         get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i))
     97        get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i))
    10898#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
    109         PAGE_PRESENT
     99        PAGE_PRESENT
    110100#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
    111         PAGE_PRESENT
     101        PAGE_PRESENT
    112102#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
    113         get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i))
     103        get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i))
    114104
    115105/* Set PTE flags accessors for each level. */
    116106#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
    117         set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x))
     107        set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x))
    118108#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
    119109#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
    … …  
    129119        set_pt_level1_present((pte_t *) (ptl3), (size_t) (i))
    130120
    131 #if defined(PROCESSOR_armv6) | defined(PROCESSOR_armv7_a)
    132 #include "page_armv6.h"
    133 #elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
    134 #include "page_armv4.h"
    135 #else
    136 #error "Unsupported architecture"
     121/* Macros for querying the last-level PTE entries. */
     122#define PTE_VALID_ARCH(pte) \
     123        (*((uint32_t *) (pte)) != 0)
     124#define PTE_PRESENT_ARCH(pte) \
     125        (((pte_t *) (pte))->l0.descriptor_type != 0)
     126#define PTE_GET_FRAME_ARCH(pte) \
     127        (((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH)
     128#define PTE_WRITABLE_ARCH(pte) \
     129        (((pte_t *) (pte))->l1.access_permission_0 == PTE_AP_USER_RW_KERNEL_RW)
     130#define PTE_EXECUTABLE_ARCH(pte) \
     131        1
     132
     133#ifndef __ASM__
     134
     135/** Level 0 page table entry. */
     136typedef struct {
     137        /* 0b01 for coarse tables, see below for details */
     138        unsigned descriptor_type : 2;
     139        unsigned impl_specific : 3;
     140        unsigned domain : 4;
     141        unsigned should_be_zero : 1;
     142
     143        /* Pointer to the coarse 2nd level page table (holding entries for small
     144         * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page
     145         * tables that may hold even tiny pages (1KB) but they are bigger (4KB
     146         * per table in comparison with 1KB per the coarse table)
     147         */
     148        unsigned coarse_table_addr : 22;
     149} ATTRIBUTE_PACKED pte_level0_t;
     150
     151/** Level 1 page table entry (small (4KB) pages used). */
     152typedef struct {
     153
     154        /* 0b10 for small pages */
     155        unsigned descriptor_type : 2;
     156        unsigned bufferable : 1;
     157        unsigned cacheable : 1;
     158
     159        /* access permissions for each of 4 subparts of a page
     160         * (for each 1KB when small pages used */
     161        unsigned access_permission_0 : 2;
     162        unsigned access_permission_1 : 2;
     163        unsigned access_permission_2 : 2;
     164        unsigned access_permission_3 : 2;
     165        unsigned frame_base_addr : 20;
     166} ATTRIBUTE_PACKED pte_level1_t;
     167
     168typedef union {
     169        pte_level0_t l0;
     170        pte_level1_t l1;
     171} pte_t;
     172
     173/* Level 1 page tables access permissions */
     174
     175/** User mode: no access, privileged mode: no access. */
     176#define PTE_AP_USER_NO_KERNEL_NO        0
     177
     178/** User mode: no access, privileged mode: read/write. */
     179#define PTE_AP_USER_NO_KERNEL_RW        1
     180
     181/** User mode: read only, privileged mode: read/write. */
     182#define PTE_AP_USER_RO_KERNEL_RW        2
     183
     184/** User mode: read/write, privileged mode: read/write. */
     185#define PTE_AP_USER_RW_KERNEL_RW        3
     186
     187
     188/* pte_level0_t and pte_level1_t descriptor_type flags */
     189
     190/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */
     191#define PTE_DESCRIPTOR_NOT_PRESENT      0
     192
     193/** pte_level0_t coarse page table flag (used in descriptor_type). */
     194#define PTE_DESCRIPTOR_COARSE_TABLE     1
     195
     196/** pte_level1_t small page table flag (used in descriptor type). */
     197#define PTE_DESCRIPTOR_SMALL_PAGE       2
     198
     199
     200/** Sets the address of level 0 page table.
     201 *
     202 * @param pt Pointer to the page table to set.
     203 *
     204 */
     205NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
     206{
     207        asm volatile (
     208                "mcr p15, 0, %[pt], c2, c0, 0\n"
     209                :: [pt] "r" (pt)
     210        );
     211}
     212
     213
     214/** Returns level 0 page table entry flags.
     215 *
     216 * @param pt Level 0 page table.
     217 * @param i  Index of the entry to return.
     218 *
     219 */
     220NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i)
     221{
     222        pte_level0_t *p = &pt[i].l0;
     223        int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT);
     224       
     225        return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) |
     226            (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) |
     227            (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT);
     228}
     229
     230/** Returns level 1 page table entry flags.
     231 *
     232 * @param pt Level 1 page table.
     233 * @param i  Index of the entry to return.
     234 *
     235 */
     236NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i)
     237{
     238        pte_level1_t *p = &pt[i].l1;
     239       
     240        int dt = p->descriptor_type;
     241        int ap = p->access_permission_0;
     242       
     243        return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) |
     244            ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) |
     245            ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT) |
     246            ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT) |
     247            ((ap != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT) |
     248            ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT) |
     249            ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT) |
     250            (1 << PAGE_EXEC_SHIFT) |
     251            (p->bufferable << PAGE_CACHEABLE);
     252}
     253
     254/** Sets flags of level 0 page table entry.
     255 *
     256 * @param pt    level 0 page table
     257 * @param i     index of the entry to be changed
     258 * @param flags new flags
     259 *
     260 */
     261NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags)
     262{
     263        pte_level0_t *p = &pt[i].l0;
     264       
     265        if (flags & PAGE_NOT_PRESENT) {
     266                p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
     267                /*
     268                 * Ensures that the entry will be recognized as valid when
     269                 * PTE_VALID_ARCH applied.
     270                 */
     271                p->should_be_zero = 1;
     272        } else {
     273                p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
     274                p->should_be_zero = 0;
     275        }
     276}
     277
     278NO_TRACE static inline void set_pt_level0_present(pte_t *pt, size_t i)
     279{
     280        pte_level0_t *p = &pt[i].l0;
     281
     282        p->should_be_zero = 0;
     283        write_barrier();
     284        p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
     285}
     286
     287/** Sets flags of level 1 page table entry.
     288 *
     289 * We use same access rights for the whole page. When page
     290 * is not preset we store 1 in acess_rigts_3 so that at least
     291 * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH).
     292 *
     293 * @param pt    Level 1 page table.
     294 * @param i     Index of the entry to be changed.
     295 * @param flags New flags.
     296 *
     297 */
     298NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags)
     299{
     300        pte_level1_t *p = &pt[i].l1;
     301       
     302        if (flags & PAGE_NOT_PRESENT)
     303                p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
     304        else
     305                p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
     306       
     307        p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
     308       
     309        /* default access permission */
     310        p->access_permission_0 = p->access_permission_1 =
     311            p->access_permission_2 = p->access_permission_3 =
     312            PTE_AP_USER_NO_KERNEL_RW;
     313       
     314        if (flags & PAGE_USER)  {
     315                if (flags & PAGE_READ) {
     316                        p->access_permission_0 = p->access_permission_1 =
     317                            p->access_permission_2 = p->access_permission_3 =
     318                            PTE_AP_USER_RO_KERNEL_RW;
     319                }
     320                if (flags & PAGE_WRITE) {
     321                        p->access_permission_0 = p->access_permission_1 =
     322                            p->access_permission_2 = p->access_permission_3 =
     323                            PTE_AP_USER_RW_KERNEL_RW;
     324                }
     325        }
     326}
     327
     328NO_TRACE static inline void set_pt_level1_present(pte_t *pt, size_t i)
     329{
     330        pte_level1_t *p = &pt[i].l1;
     331
     332        p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
     333}
     334       
     335extern void page_arch_init(void);
     336
     337#endif /* __ASM__ */
     338
    137339#endif
    138340
    139 #endif
    140 
    141341/** @}
    142342 */

  • kernel/arch/arm32/include/mm/page_fault.h

    rb3ab8f7 raac1c417  
    4040
    4141
    42 /** Decribes CP15 "fault status register" (FSR).
    43  *
    44  * See ARM Architecture Reference Manual ch. B4.9.6 (pdf p.743).
    45  */
     42/** Decribes CP15 "fault status register" (FSR). */
     43typedef struct {
     44        unsigned status : 3;
     45        unsigned domain : 4;
     46        unsigned zero : 1;
     47        unsigned should_be_zero : 24;
     48} ATTRIBUTE_PACKED fault_status_t;
     49
     50
     51/** Help union used for casting integer value into #fault_status_t. */
    4652typedef union {
    47         struct {
    48                 unsigned status : 4;
    49                 unsigned domain : 4;
    50                 unsigned zero : 1;
    51                 unsigned lpae : 1; /**< Needs LPAE support implemented */
    52                 unsigned fs : 1; /**< armv6+ mandated, earlier IPLM. DEFINED */
    53                 unsigned wr : 1; /**< armv6+ only */
    54                 unsigned ext : 1 ; /**< external abort */
    55                 unsigned cm : 1; /**< Cache maintenance, needs LPAE support */
    56                 unsigned should_be_zero : 18;
    57         } data;
    58         struct {
    59                 unsigned status : 4;
    60                 unsigned sbz0 : 6;
    61                 unsigned fs : 1;
    62                 unsigned should_be_zero : 21;
    63         } inst;
    64         uint32_t raw;
    65 } fault_status_t;
     53        fault_status_t fs;
     54        uint32_t dummy;
     55} fault_status_union_t;
    6656
    6757

  • kernel/arch/arm32/include/regutils.h

    rb3ab8f7 raac1c417  
    4141#define STATUS_REG_MODE_MASK         0x1f
    4242
    43 /* COntrol register bit values see ch. B4.1.130 of ARM Architecture Reference
    44  * Manual ARMv7-A and ARMv7-R edition, page 1687 */
    45 #define CP15_R1_MMU_EN            (1 << 0)
    46 #define CP15_R1_ALIGN_CHECK_EN    (1 << 1)  /* Allow alignemnt check */
    47 #define CP15_R1_CACHE_EN          (1 << 2)
    48 #define CP15_R1_CP15_BARRIER_EN   (1 << 5)
    49 #define CP15_R1_B_EN              (1 << 7)  /* ARMv6- only big endian switch */
    50 #define CP15_R1_SWAP_EN           (1 << 10)
    51 #define CP15_R1_BRANCH_PREDICT_EN (1 << 11)
    52 #define CP15_R1_INST_CACHE_EN     (1 << 12)
    53 #define CP15_R1_HIGH_VECTORS_EN   (1 << 13)
    54 #define CP15_R1_ROUND_ROBIN_EN    (1 << 14)
    55 #define CP15_R1_HW_ACCESS_FLAG_EN (1 << 17)
    56 #define CP15_R1_WRITE_XN_EN       (1 << 19) /* Only if virt. supported */
    57 #define CP15_R1_USPCE_WRITE_XN_EN (1 << 20) /* Only if virt. supported */
    58 #define CP15_R1_FAST_IRQ_EN       (1 << 21) /* Disbale impl.specific features */
    59 #define CP15_R1_UNALIGNED_EN      (1 << 22) /* Must be 1 on armv7 */
    60 #define CP15_R1_IRQ_VECTORS_EN    (1 << 24)
    61 #define CP15_R1_BIG_ENDIAN_EXC    (1 << 25)
    62 #define CP15_R1_NMFI_EN           (1 << 27)
    63 #define CP15_R1_TEX_REMAP_EN      (1 << 28)
    64 #define CP15_R1_ACCESS_FLAG_EN    (1 << 29)
    65 #define CP15_R1_THUMB_EXC_EN      (1 << 30)
     43#define CP15_R1_HIGH_VECTORS_BIT     (1 << 13)
    6644
    6745/* ARM Processor Operation Modes */

  • kernel/arch/arm32/src/arm32.c

    rb3ab8f7 raac1c417  
    4949#include <str.h>
    5050#include <arch/ras.h>
    51 #include <sysinfo/sysinfo.h>
    5251
    5352/** Performs arm32-specific initialization before main_bsp() is called. */
    … …  
    117116{
    118117        machine_input_init();
    119         const char *platform = machine_get_platform_name();
    120 
    121         sysinfo_set_item_data("platform", NULL, (void *) platform,
    122             str_size(platform));
    123118}
    124119

  • kernel/arch/arm32/src/cpu/cpu.c

    rb3ab8f7 raac1c417  
    4444/** Implementators (vendor) names */
    4545static const char *imp_data[] = {
    46         "?",                                     /* IMP_DATA_START_OFFSET */
    47         "ARM Limited",                           /* 0x41 */
    48         "", "",                                  /* 0x42 - 0x43 */
    49         "Digital Equipment Corporation",         /* 0x44 */
    50         "", "", "", "", "", "", "", "",          /* 0x45 - 0x4c */
    51         "Motorola, Freescale Semicondutor Inc.", /* 0x4d */
    52         "", "", "",                              /* 0x4e - 0x50 */
    53         "Qualcomm Inc.",                         /* 0x51 */
    54         "", "", "", "",                          /* 0x52 - 0x55 */
    55         "Marvell Semiconductor",                 /* 0x56 */
    56         "", "", "", "", "", "", "", "", "", "",  /* 0x57 - 0x60 */
    57         "", "", "", "", "", "", "", "",          /* 0x61 - 0x68 */
    58         "Intel Corporation"                      /* 0x69 */
     46        "?",                                    /* IMP_DATA_START_OFFSET */
     47        "ARM Ltd",                              /* 0x41 */
     48        "",                                     /* 0x42 */
     49        "",                                     /* 0x43 */
     50        "Digital Equipment Corporation",        /* 0x44 */
     51        "", "", "", "", "", "", "", "", "", "", /* 0x45 - 0x4e */
     52        "", "", "", "", "", "", "", "", "", "", /* 0x4f - 0x58 */
     53        "", "", "", "", "", "", "", "", "", "", /* 0x59 - 0x62 */
     54        "", "", "", "", "", "",                 /* 0x63 - 0x68 */
     55        "Intel Corporation"                     /* 0x69 */
    5956};
    6057
    … …  
    9794}
    9895
    99 /** Enables unaligned access and caching for armv6+ */
     96/** Does nothing on ARM. */
    10097void cpu_arch_init(void)
    10198{
    102 #if defined(PROCESSOR_armv7_a) | defined(PROCESSOR_armv6)
    103         uint32_t control_reg = 0;
    104         asm volatile (
    105                 "mrc p15, 0, %[control_reg], c1, c0"
    106                 : [control_reg] "=r" (control_reg)
    107         );
    108        
    109         /* Turn off tex remap, RAZ ignores writes prior to armv7 */
    110         control_reg &= ~CP15_R1_TEX_REMAP_EN;
    111         /* Turn off accessed flag, RAZ ignores writes prior to armv7 */
    112         control_reg &= ~(CP15_R1_ACCESS_FLAG_EN | CP15_R1_HW_ACCESS_FLAG_EN);
    113         /* Enable unaligned access, RAZ ignores writes prior to armv6
    114          * switchable on armv6, RAO ignores writes on armv7,
    115          * see ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
    116          * L.3.1 (p. 2456) */
    117         control_reg |= CP15_R1_UNALIGNED_EN;
    118         /* Disable alignment checks, this turns unaligned access to undefined,
    119          * unless U bit is set. */
    120         control_reg &= ~CP15_R1_ALIGN_CHECK_EN;
    121         /* Enable caching, On arm prior to armv7 there is only one level
    122          * of caches. Data cache is coherent.
    123          * "This means that the behavior of accesses from the same observer to
    124          * different VAs, that are translated to the same PA
    125          * with the same memory attributes, is fully coherent."
    126          *    ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition
    127          *    B3.11.1 (p. 1383)
    128          * ICache coherency is elaborate on in barrier.h.
    129          * We are safe to turn these on.
    130          */
    131         control_reg |= CP15_R1_CACHE_EN | CP15_R1_INST_CACHE_EN;
    132        
    133         asm volatile (
    134                 "mcr p15, 0, %[control_reg], c1, c0"
    135                 :: [control_reg] "r" (control_reg)
    136         );
    137 #endif
    13899}
    139100
    140101/** Retrieves processor identification and stores it to #CPU.arch */
    141 void cpu_identify(void)
     102void cpu_identify(void) 
    142103{
    143104        arch_cpu_identify(&CPU->arch);
    … …  
    151112        cpu_arch_t * cpu_arch = &m->arch;
    152113
    153         const unsigned imp_offset = cpu_arch->imp_num - IMP_DATA_START_OFFSET;
    154 
    155         if (imp_offset < imp_data_length) {
     114        if ((cpu_arch->imp_num) > 0 &&
     115            (cpu_arch->imp_num < (imp_data_length + IMP_DATA_START_OFFSET))) {
    156116                vendor = imp_data[cpu_arch->imp_num - IMP_DATA_START_OFFSET];
    157117        }
    158118
    159         // TODO CPUs with arch_num == 0xf use CPUID scheme for identification
    160         if (cpu_arch->arch_num < arch_data_length) {
     119        if ((cpu_arch->arch_num) > 0 &&
     120            (cpu_arch->arch_num < arch_data_length)) {
    161121                architecture = arch_data[cpu_arch->arch_num];
    162122        }

  • kernel/arch/arm32/src/exception.c

    rb3ab8f7 raac1c417  
    117117
    118118#ifdef HIGH_EXCEPTION_VECTORS
    119 /** Activates use of high exception vectors addresses.
    120  *
    121  * "High vectors were introduced into some implementations of ARMv4 and are
    122  * required in ARMv6 implementations. High vectors allow the exception vector
    123  * locations to be moved from their normal address range 0x00000000-0x0000001C
    124  * at the bottom of the 32-bit address space, to an alternative address range
    125  * 0xFFFF0000-0xFFFF001C near the top of the address space. These alternative
    126  * locations are known as the high vectors.
    127  *
    128  * Prior to ARMv6, it is IMPLEMENTATION DEFINED whether the high vectors are
    129  * supported. When they are, a hardware configuration input selects whether
    130  * the normal vectors or the high vectors are to be used from
    131  * reset." ARM Architecture Reference Manual A2.6.11 (p. 64 in the PDF).
    132  *
    133  * ARM920T (gta02) TRM A2.3.5 (PDF p. 36) and ARM926EJ-S (icp) 2.3.2 (PDF p. 42)
    134  * say that armv4 an armv5 chips that we support implement this.
    135  */
     119/** Activates use of high exception vectors addresses. */
    136120static void high_vectors(void)
    137121{
    138         uint32_t control_reg = 0;
     122        uint32_t control_reg;
     123       
    139124        asm volatile (
    140125                "mrc p15, 0, %[control_reg], c1, c0"
    … …  
    143128       
    144129        /* switch on the high vectors bit */
    145         control_reg |= CP15_R1_HIGH_VECTORS_EN;
     130        control_reg |= CP15_R1_HIGH_VECTORS_BIT;
    146131       
    147132        asm volatile (
    … …  
    168153void exception_init(void)
    169154{
    170         // TODO check for availability of high vectors for <= armv5
    171155#ifdef HIGH_EXCEPTION_VECTORS
    172156        high_vectors();

  • kernel/arch/arm32/src/machine_func.c

    rb3ab8f7 raac1c417  
    4242#include <arch/mach/integratorcp/integratorcp.h>
    4343#include <arch/mach/testarm/testarm.h>
    44 #include <arch/mach/beagleboardxm/beagleboardxm.h>
    4544
    4645/** Pointer to machine_ops structure being used. */
    … …  
    5655#elif defined(MACHINE_integratorcp)
    5756        machine_ops = &icp_machine_ops;
    58 #elif defined(MACHINE_beagleboardxm)
    59         machine_ops = &bbxm_machine_ops;
    6057#else
    6158#error Machine type not defined.
    … …  
    134131}
    135132
    136 const char * machine_get_platform_name(void)
    137 {
    138         if (machine_ops->machine_get_platform_name)
    139                 return machine_ops->machine_get_platform_name();
    140         return NULL;
    141 }
    142133/** @}
    143134 */

  • kernel/arch/arm32/src/mm/page.c

    rb3ab8f7 raac1c417  
    5252void page_arch_init(void)
    5353{
    54         int flags = PAGE_CACHEABLE | PAGE_EXEC;
     54        int flags = PAGE_CACHEABLE;
    5555        page_mapping_operations = &pt_mapping_operations;
    5656
    5757        page_table_lock(AS_KERNEL, true);
    5858       
     59        uintptr_t cur;
     60
    5961        /* Kernel identity mapping */
    60         //FIXME: We need to consider the possibility that
    61         //identity_base > identity_size and physmem_end.
    62         //This might lead to overflow if identity_size is too big.
    63         for (uintptr_t cur = PHYSMEM_START_ADDR;
    64             cur < min(KA2PA(config.identity_base) +
    65                 config.identity_size, config.physmem_end);
     62        for (cur = PHYSMEM_START_ADDR;
     63            cur < min(config.identity_size, config.physmem_end);
    6664            cur += FRAME_SIZE)
    6765                page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags);

  • kernel/arch/arm32/src/mm/page_fault.c

    rb3ab8f7 raac1c417  
    4242#include <print.h>
    4343
    44 
    45 /**
    46  * FSR encoding ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition.
     44/** Returns value stored in fault status register.
    4745 *
    48  * B3.13.3 page B3-1406 (PDF page 1406)
     46 *  @return Value stored in CP15 fault status register (FSR).
    4947 */
    50 typedef enum {
    51         DFSR_SOURCE_ALIGN = 0x0001,
    52         DFSR_SOURCE_CACHE_MAINTENANCE = 0x0004,
    53         DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1 = 0x000c,
    54         DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2 = 0x000e,
    55         DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1 = 0x040c,
    56         DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2 = 0x040e,
    57         DFSR_SOURCE_TRANSLATION_L1 = 0x0005,
    58         DFSR_SOURCE_TRANSLATION_L2 = 0x0007,
    59         DFSR_SOURCE_ACCESS_FLAG_L1 = 0x0003,  /**< @note: This used to be alignment enc. */
    60         DFSR_SOURCE_ACCESS_FLAG_L2 = 0x0006,
    61         DFSR_SOURCE_DOMAIN_L1 = 0x0009,
    62         DFSR_SOURCE_DOMAIN_L2 = 0x000b,
    63         DFSR_SOURCE_PERMISSION_L1 = 0x000d,
    64         DFSR_SOURCE_PERMISSION_L2 = 0x000f,
    65         DFSR_SOURCE_DEBUG = 0x0002,
    66         DFSR_SOURCE_SYNC_EXTERNAL = 0x0008,
    67         DFSR_SOURCE_TLB_CONFLICT = 0x0400,
    68         DFSR_SOURCE_LOCKDOWN = 0x0404, /**< @note: Implementation defined */
    69         DFSR_SOURCE_COPROCESSOR = 0x040a, /**< @note Implementation defined */
    70         DFSR_SOURCE_SYNC_PARITY = 0x0409,
    71         DFSR_SOURCE_ASYNC_EXTERNAL = 0x0406,
    72         DFSR_SOURCE_ASYNC_PARITY = 0x0408,
    73         DFSR_SOURCE_MASK = 0x0000040f,
    74 } dfsr_source_t;
    75 
    76 static inline const char * dfsr_source_to_str(dfsr_source_t source)
     48static inline fault_status_t read_fault_status_register(void)
    7749{
    78         switch (source) {
    79         case DFSR_SOURCE_TRANSLATION_L1:
    80                 return "Translation fault L1";
    81         case DFSR_SOURCE_TRANSLATION_L2:
    82                 return "Translation fault L2";
    83         case DFSR_SOURCE_PERMISSION_L1:
    84                 return "Permission fault L1";
    85         case DFSR_SOURCE_PERMISSION_L2:
    86                 return "Permission fault L2";
    87         case DFSR_SOURCE_ALIGN:
    88                 return "Alignment fault";
    89         case DFSR_SOURCE_CACHE_MAINTENANCE:
    90                 return "Instruction cache maintenance fault";
    91         case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1:
    92                 return "Synchronous external abort on translation table walk level 1";
    93         case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2:
    94                 return "Synchronous external abort on translation table walk level 2";
    95         case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1:
    96                 return "Synchronous parity error on translation table walk level 1";
    97         case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2:
    98                 return "Synchronous parity error on translation table walk level 2";
    99         case DFSR_SOURCE_ACCESS_FLAG_L1:
    100                 return "Access flag fault L1";
    101         case DFSR_SOURCE_ACCESS_FLAG_L2:
    102                 return "Access flag fault L2";
    103         case DFSR_SOURCE_DOMAIN_L1:
    104                 return "Domain fault L1";
    105         case DFSR_SOURCE_DOMAIN_L2:
    106                 return "Domain flault L2";
    107         case DFSR_SOURCE_DEBUG:
    108                 return "Debug event";
    109         case DFSR_SOURCE_SYNC_EXTERNAL:
    110                 return "Synchronous external abort";
    111         case DFSR_SOURCE_TLB_CONFLICT:
    112                 return "TLB conflict abort";
    113         case DFSR_SOURCE_LOCKDOWN:
    114                 return "Lockdown (Implementation defined)";
    115         case DFSR_SOURCE_COPROCESSOR:
    116                 return "Coprocessor abort (Implementation defined)";
    117         case DFSR_SOURCE_SYNC_PARITY:
    118                 return "Synchronous parity error on memory access";
    119         case DFSR_SOURCE_ASYNC_EXTERNAL:
    120                 return "Asynchronous external abort";
    121         case DFSR_SOURCE_ASYNC_PARITY:
    122                 return "Asynchronous parity error on memory access";
    123         case DFSR_SOURCE_MASK:
    124                 break;
    125         }
    126         return "Unknown data abort";
     50        fault_status_union_t fsu;
     51       
     52        /* fault status is stored in CP15 register 5 */
     53        asm volatile (
     54                "mrc p15, 0, %[dummy], c5, c0, 0"
     55                : [dummy] "=r" (fsu.dummy)
     56        );
     57       
     58        return fsu.fs;
    12759}
    12860
    129 
    130 /** Returns value stored in comnbined/data fault status register.
     61/** Returns FAR (fault address register) content.
    13162 *
    132  *  @return Value stored in CP15 fault status register (FSR).
    133  *
    134  *  "VMSAv6 added a fifth fault status bit (bit[10]) to both the IFSR and DFSR.
    135  *  It is IMPLEMENTATION DEFINED how this bit is encoded in earlier versions of
    136  *  the architecture. A write flag (bit[11] of the DFSR) has also been
    137  *  introduced."
    138  *  ARM Architecture Reference Manual version i ch. B4.6 (PDF p. 719)
    139  *
    140  *  See ch. B4.9.6 for location of data/instruction FSR.
    141  *
    142  */
    143 static inline fault_status_t read_data_fault_status_register(void)
    144 {
    145         fault_status_t fsu;
    146        
    147         /* Combined/Data fault status is stored in CP15 register 5, c0. */
    148         asm volatile (
    149                 "mrc p15, 0, %[dummy], c5, c0, 0"
    150                 : [dummy] "=r" (fsu.raw)
    151         );
    152        
    153         return fsu;
    154 }
    155 
    156 /** Returns DFAR (fault address register) content.
    157  *
    158  * This register is equivalent to FAR on pre armv6 machines.
    159  *
    160  * @return DFAR (fault address register) content (address that caused a page
     63 * @return FAR (fault address register) content (address that caused a page
    16164 *         fault)
    16265 */
    163 static inline uintptr_t read_data_fault_address_register(void)
     66static inline uintptr_t read_fault_address_register(void)
    16467{
    16568        uintptr_t ret;
    … …  
    17477}
    17578
    176 #if defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
    17779/** Decides whether read or write into memory is requested.
    17880 *
    … …  
    19597                panic("page_fault - instruction does not access memory "
    19698                    "(instr_code: %#0" PRIx32 ", badvaddr:%p).",
    197                     *(uint32_t*)instr_union.instr, (void *) badvaddr);
     99                    instr_union.pc, (void *) badvaddr);
    198100                return PF_ACCESS_EXEC;
    199101        }
    … …  
    234136            inst, (void *) badvaddr);
    235137}
    236 #endif
    237138
    238139/** Handles "data abort" exception (load or store at invalid address).
    … …  
    244145void data_abort(unsigned int exc_no, istate_t *istate)
    245146{
    246         const uintptr_t badvaddr = read_data_fault_address_register();
    247         const fault_status_t fsr = read_data_fault_status_register();
    248         const dfsr_source_t source = fsr.raw & DFSR_SOURCE_MASK;
     147        fault_status_t fsr __attribute__ ((unused)) =
     148            read_fault_status_register();
     149        uintptr_t badvaddr = read_fault_address_register();
    249150
    250         switch (source) {
    251         case DFSR_SOURCE_TRANSLATION_L1:
    252         case DFSR_SOURCE_TRANSLATION_L2:
    253         case DFSR_SOURCE_PERMISSION_L1:
    254         case DFSR_SOURCE_PERMISSION_L2:
    255                 /* Page fault is handled further down */
    256                 break;
    257         case DFSR_SOURCE_ALIGN:
    258         case DFSR_SOURCE_CACHE_MAINTENANCE:
    259         case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1:
    260         case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2:
    261         case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1:
    262         case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2:
    263         case DFSR_SOURCE_ACCESS_FLAG_L1:
    264         case DFSR_SOURCE_ACCESS_FLAG_L2:
    265         case DFSR_SOURCE_DOMAIN_L1:
    266         case DFSR_SOURCE_DOMAIN_L2:
    267         case DFSR_SOURCE_DEBUG:
    268         case DFSR_SOURCE_SYNC_EXTERNAL:
    269         case DFSR_SOURCE_TLB_CONFLICT:
    270         case DFSR_SOURCE_LOCKDOWN:
    271         case DFSR_SOURCE_COPROCESSOR:
    272         case DFSR_SOURCE_SYNC_PARITY:
    273         case DFSR_SOURCE_ASYNC_EXTERNAL:
    274         case DFSR_SOURCE_ASYNC_PARITY:
    275         case DFSR_SOURCE_MASK:
    276                 /* Weird abort stuff */
    277                 fault_if_from_uspace(istate, "Unhandled abort %s at address: "
    278                     "%#x.", dfsr_source_to_str(source), badvaddr);
    279                 panic("Unhandled abort %s at address: %#x.",
    280                     dfsr_source_to_str(source), badvaddr);
    281         }
     151        pf_access_t access = get_memory_access_type(istate->pc, badvaddr);
    282152
    283 #if defined(PROCESSOR_armv6) | defined(PROCESSOR_armv7_a)
    284         const pf_access_t access =
    285             fsr.data.wr ? PF_ACCESS_WRITE : PF_ACCESS_READ;
    286 #elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
    287         const pf_access_t access = get_memory_access_type(istate->pc, badvaddr);
    288 #else
    289 #error "Unsupported architecture"
    290 #endif
    291         const int ret = as_page_fault(badvaddr, access, istate);
     153        int ret = as_page_fault(badvaddr, access, istate);
    292154
    293155        if (ret == AS_PF_FAULT) {
    … …  
    305167void prefetch_abort(unsigned int exc_no, istate_t *istate)
    306168{
    307         /* NOTE: We should use IFAR and IFSR here. */
    308169        int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate);
    309170

  • kernel/genarch/Makefile.inc

    rb3ab8f7 raac1c417  
    106106endif
    107107
    108 ifeq ($(CONFIG_AMDM37X_UART),y)
    109         GENARCH_SOURCES += \
    110                 genarch/src/drivers/amdm37x_uart/amdm37x_uart.c
    111 endif
    112 
    113108ifeq ($(CONFIG_VIA_CUDA),y)
    114109        GENARCH_SOURCES += \

  • tools/mkuimage.py

    rb3ab8f7 raac1c417  
    6060        load_addr = 0
    6161        start_addr = 0
    62         os_type = 5 #Linux is the default
    6362
    6463        while len(args) >= 2 and args[0][0] == '-':
    … …  
    7271                elif opt == 'saddr':
    7372                        start_addr = (int)(optarg, 0)
    74                 elif opt == 'ostype':
    75                         os_type = (int)(optarg, 0)
    7673                else:
    7774                        print(base_name + ": Unrecognized option.")
    … …  
    8885
    8986        try:
    90                 mkuimage(inf_name, outf_name, image_name, load_addr, start_addr, os_type)
     87                mkuimage(inf_name, outf_name, image_name, load_addr, start_addr)
    9188        except:
    9289                os.remove(outf_name)
    9390                raise
    9491
    95 def mkuimage(inf_name, outf_name, image_name, load_addr, start_addr, os_type):
     92def mkuimage(inf_name, outf_name, image_name, load_addr, start_addr):
    9693        inf = open(inf_name, 'rb')
    9794        outf = open(outf_name, 'wb')
    … …  
    123120        header.start_addr = start_addr  # Address of entry point
    124121        header.data_crc = data_crc
    125         header.os = os_type
     122        header.os = 5                   # Linux
    126123        header.arch = 2                 # ARM
    127124        header.img_type = 2             # Kernel

  • uspace/Makefile

    rb3ab8f7 raac1c417  
    194194endif
    195195
    196 ifeq ($(UARCH),arm32)
    197         DIRS += \
    198                 drv/infrastructure/rootamdm37x
    199 endif
    200 
    201196## System libraries
    202197#

  • uspace/drv/bus/usb/ehci/ehci.ma

    rb3ab8f7 raac1c417  
    1 20 usb/host=ehci
    2110 pci/class=0c&subclass=03&progif=20

  • uspace/drv/bus/usb/ohci/ohci.ma

    rb3ab8f7 raac1c417  
    1 20 usb/host=ohci
    2110 pci/class=0c&subclass=03&progif=10

  • uspace/drv/bus/usb/ohci/ohci_regs.h

    rb3ab8f7 raac1c417  
    245245#define RHPS_PRSC_FLAG (1 << 20) /* port reset status change WC */
    246246#define RHPS_CHANGE_WC_MASK (0x1f0000)
    247 } ohci_regs_t;
     247} __attribute__((packed)) ohci_regs_t;
    248248#endif
    249249/**

  • uspace/lib/c/arch/arm32/Makefile.common

    rb3ab8f7 raac1c417  
    2929
    3030BASE_LIBS += $(LIBSOFTFLOAT_PREFIX)/libsoftfloat.a
    31 GCC_CFLAGS += -ffixed-r9 -mtp=soft -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR))
     31GCC_CFLAGS += -ffixed-r9 -mtp=soft -fno-omit-frame-pointer -march=armv4 -mapcs-frame
    3232
    3333ENDIANESS = LE

  • uspace/lib/c/include/macros.h

    rb3ab8f7 raac1c417  
    6060#endif
    6161
    62 #define _paddname(line) PADD_ ## line ## __
    63 #define _padd(width, line) uint ## width ## _t _paddname(line)
    64 #define PADD32(count) _padd(32, __LINE__)[count]
    65 #define PADD16(count) _padd(16, __LINE__)[count]
    66 #define PADD8(count) _padd(8, __LINE__)[count]
    67 
    6862/** @}
    6963 */

  • uspace/lib/usbdev/include/usb/dev/request.h

    rb3ab8f7 raac1c417  
    9393        uint8_t request;
    9494        /** Main parameter to the request. */
    95         union __attribute__ ((packed)) {
     95        union {
    9696                uint16_t value;
    9797                /* FIXME: add #ifdefs according to host endianness */
    98                 struct __attribute__ ((packed)) {
     98                struct {
    9999                        uint8_t value_low;
    100100                        uint8_t value_high;
    … …  
    108108        uint16_t length;
    109109} __attribute__ ((packed)) usb_device_request_setup_packet_t;
    110 
    111 int assert[(sizeof(usb_device_request_setup_packet_t) == 8) ? 1: -1];
    112110
    113111int usb_control_request_set(usb_pipe_t *,
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