Changeset ab1ae2d9 in mainline

Timestamp:

2006-09-09T09:29:50Z (18 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

27ab6a7

Parents:

253f35a1

Message:

Fixes for sparc64's preemptible_handler().
Resynchronize CWP with that of TL=0.

File:

• kernel/arch/sparc64/src/trap/trap_table.S (modified) (3 diffs)

kernel/arch/sparc64/src/trap/trap_table.S

@@ -586 +586 @@
         be 1f
         nop
-0:      ba 0b                                   ! this for debugging, if we ever get here
+0:      ba 0b                                   ! this is for debugging, if we ever get here
         nop                                     ! it will be easy to find
 
@@ -592 +592 @@
 .if NOT(\is_syscall)
         rdpr %tstate, %g3
+        
+        /*
+         * One of the ways this handler can be invoked is after a nested MMU trap from
+         * either spill_1_normal or fill_1_normal traps. Both of these traps manipulate
+         * the CWP register. We deal with the situation by simulating the MMU trap
+         * on TL=1 and restart the respective SAVE or RESTORE instruction once the MMU
+         * trap is resolved. However, because we are in the wrong window from the
+         * perspective of the MMU trap, we need to synchronize CWP with CWP from TL=0.
+         */ 
+        and %g3, TSTATE_CWP_MASK, %g4
+        wrpr %g4, 0, %cwp                       ! resynchronize CWP
+
         andcc %g3, TSTATE_PRIV_BIT, %g0         ! if this trap came from the privileged mode...
         bnz 0f                                  ! ...skip setting of kernel stack and primary context
         nop
+        
 .endif
         /*
@@ -886 +899 @@
          *      OTHERWIN        = 0
          *
-         * The RESTORE isntruction is therfore to be skipped.
+         * The RESTORE instruction is therfore to be skipped.
          */
 2: