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  • boot/arch/arm32/src/asm.S

    rb5a3b50 rab63b04e  
    6060        # before passing control to the copied code.
    6161        #
    62 
    63 #if defined(MACHINE_gta02)
    64 
    65 #define CP15_C1_IC              12
    66 #define CP15_C1_DC              2
    67 #define CP15_C7_SEG_SHIFT       5
    68 #define CP15_C7_SEG_SIZE        3
    69 #define CP15_C7_IDX_SHIFT       26
    70 
    71         # Disable I-cache and D-cache before the kernel is started.
    72         mrc     p15, 0, r4, c1, c0, 0
    73         bic     r4, r4, #(1 << CP15_C1_DC)
    74         bic     r4, r4, #(1 << CP15_C1_IC)
    75         mcr     p15, 0, r4, c1, c0, 0
    76 
    77         # Now clean D-cache to guarantee coherency between I-cache and D-cache.
    78 
    79         # D-cache clean and invalidate procedure.
    80         # See ARM920T TRM pages 2-17, 4-17.
    81 
    82         # Initialize segment
    83         mov     r4, #0
    84         # Initialize index
    85 1:      mov     r5, #0
    86 2:      orr     r6, r4, r5
    87         # Clean and invalidate a single line
    88         mcr     p15, 0, r6, c7, c10, 2
    89         # Increment index
    90         add     r5, r5, #(1 << CP15_C7_IDX_SHIFT)
    91         cmp     r5, #0
    92         bne     2b
    93         # Increment segment
    94         add     r4, #(1 << CP15_C7_SEG_SHIFT)
    95         tst     r4, #(1 << (CP15_C7_SEG_SHIFT + CP15_C7_SEG_SIZE))
    96         beq     1b
    97 #endif
    98 
    9962        mov pc, r0
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